linux-toradex.git/arch/arm/include, branch tegra-10.8.3 Linux kernel for Apalis and Colibri modules [tegra/arm] Use inner shareable I-cache BTB on SMP 2010-09-01T17:53:12+00:00 Jon Mayo jmayo@nvidia.com 2010-08-31T20:27:41+00:00 652c4abaaa5e9dea1468610740e1761fea4f1517 merge of the following two patches: ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MP This patch fixes the flush_cache_all for ARMv7 SMP.It was missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c Change-Id: Ie98623b758f8d2d5dabc436ab536ed83efed59f4 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-on: http://git-master/r/5826 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
merge of the following two patches:

ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP

The standard I-cache Invalidate All (ICIALLU) and Branch Predication
Invalidate All (BPIALL) operations are not automatically broadcast to
the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable
variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MP

This patch fixes the flush_cache_all for ARMv7 SMP.It was
missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c

Change-Id: Ie98623b758f8d2d5dabc436ab536ed83efed59f4
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: <stable@kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-on: http://git-master/r/5826
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
ARM: atomic ops: add memory constraints to inline asm 2010-07-09T02:34:14+00:00 Gary King gking@nvidia.com 2010-07-08T00:59:19+00:00 5512cf1b8aa256416a4943545642e7bb6766b039 add memory constraints to the rmw parameters in barrier-less atomic operations (atomic_add, atomic_sub, etc.), so that optimizing compilers do not constant-fold expressions surrounding these operations. based on a patch submitted to lakml by Will Deacon (will.deacon@arm.com) Change-Id: Idfc10bbda9b4a26ee8af6b3281075c4387e8c11f Reviewed-on: http://git-master/r/3649 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
add memory constraints to the rmw parameters in barrier-less
atomic operations (atomic_add, atomic_sub, etc.), so that
optimizing compilers do not constant-fold expressions surrounding
these operations.

based on a patch submitted to lakml by Will
Deacon (will.deacon@arm.com)

Change-Id: Idfc10bbda9b4a26ee8af6b3281075c4387e8c11f
Reviewed-on: http://git-master/r/3649
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
ARM: Convert VFP/Crunch/XscaleCP thread_release() to exit_thread() 2010-06-16T04:35:19+00:00 Russell King rmk+kernel@arm.linux.org.uk 2009-12-18T14:34:43+00:00 5648a3bbc09b7c4b404cbf52aab5fa7edbaffdf3 This avoids races in the VFP code where the dead thread may have state on another CPU. By moving this code to exit_thread(), we will be running as the thread, and therefore be running on the current CPU. This means that we can ensure that the only local state is accessed in the thread notifiers. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Change-Id: I195ea8ce8f5f438166b402411eaff3f33f4b2490 Reviewed-on: http://git-master/r/2731 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
This avoids races in the VFP code where the dead thread may have
state on another CPU.  By moving this code to exit_thread(), we
will be running as the thread, and therefore be running on the
current CPU.

This means that we can ensure that the only local state is accessed
in the thread notifiers.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Change-Id: I195ea8ce8f5f438166b402411eaff3f33f4b2490
Reviewed-on: http://git-master/r/2731
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[ARM] outer_cache: add outer_restart callback and l2x0 implementation 2010-06-12T00:14:52+00:00 Gary King gking@nvidia.com 2010-06-08T01:02:55+00:00 e8df23df7b474cd4612e0f2d084c55b911b2173f outer_restart should be called by platform suspend_ops to restore the outer cache to an active state following a power transition which disables or otherwise invalidates the outer cache state. Change-Id: I07a5268d1783fecd36491138e20913fca24a26d9 Reviewed-on: http://git-master/r/2243 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
outer_restart should be called by platform suspend_ops to restore
the outer cache to an active state following a power transition
which disables or otherwise invalidates the outer cache state.

Change-Id: I07a5268d1783fecd36491138e20913fca24a26d9
Reviewed-on: http://git-master/r/2243
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
[ARM] Do not call flush_cache_user_range with mmap_sem held 2010-05-23T21:43:08+00:00 Dima Zavin dima@android.com 2010-04-28T03:57:04+00:00 d383a107bd7985f458078fa342043e5835f09725 We can't be holding the mmap_sem while calling flush_cache_user_range because the flush can fault. If we fault on a user address, the page fault handler will try to take mmap_sem again. Since both places acquire the read lock, most of the time it succeeds. However, if another thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in between the call to flush_cache_user_range and the fault, the down_read in do_page_fault will deadlock. Also, since we really can't be holding the mmap_sem while calling flush_cache_user_range AND vma is actually unused by the flush itself, get rid of vma as an argument. Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106 Signed-off-by: Dima Zavin <dima@android.com> 
We can't be holding the mmap_sem while calling flush_cache_user_range
because the flush can fault. If we fault on a user address, the
page fault handler will try to take mmap_sem again. Since both places
acquire the read lock, most of the time it succeeds. However, if another
thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in
between the call to flush_cache_user_range and the fault, the down_read
in do_page_fault will deadlock.

Also, since we really can't be holding the mmap_sem while calling
flush_cache_user_range AND vma is actually unused by the flush itself,
get rid of vma as an argument.

Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106
Signed-off-by: Dima Zavin <dima@android.com>
[ARM] smp_twd: add USE_ARM_TWD_PRESCALER config 2010-05-15T03:04:14+00:00 Gary King gking@nvidia.com 2010-05-15T02:13:18+00:00 0ccee597a45f630ed551423f037def906b715ac1 the local timers support prescaling the event timeout, which can be used to efficiently update the countdown frequency to compensate for CPU frequency changes. Change-Id: Ic4d0236f39fe1b8c6d436625bf9b584c417f6f00 
the local timers support prescaling the event timeout, which
can be used to efficiently update the countdown frequency to
compensate for CPU frequency changes.

Change-Id: Ic4d0236f39fe1b8c6d436625bf9b584c417f6f00
[ARM]: add memory type for inner-WBWA, outer-non cacheable mapping 2010-05-13T03:28:44+00:00 Gary King gking@nvidia.com 2010-05-13T03:28:44+00:00 2381fc59dbf1d4256a33dd4eefb094221a55f635 For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the ARMv7 TRE table as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Id8c99e194a859865a9cff5d73eb08c451ab28f77 
For streaming-style operations (e.g., software rendering of graphics
surfaces shared with non-coherent DMA devices), the cost of performing
L2 cache maintenance can exceed the benefit of having the larger cache
(this is particularly true for OUTER_CACHE configurations like the ARM
PL2x0).

This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
in the ARMv7 TRE table as an inner-writeback-write-allocate, outer
non-cacheable memory type, so that this mapping will be available to
clients which will benefit from the reduced L2 maintenance.

Change-Id: Id8c99e194a859865a9cff5d73eb08c451ab28f77
[ARM] Add ARCH_PROVIDES_UDELAY config option 2010-05-06T03:25:12+00:00 Colin Cross ccross@android.com 2010-04-25T07:29:07+00:00 790dbc022bc62af2ee4188f9f0e38911a3032628 Change-Id: I93ded376b6b6eb4b16a9c5e1984e6753c0a8e0a1 Signed-off-by: Colin Cross <ccross@android.com> 
Change-Id: I93ded376b6b6eb4b16a9c5e1984e6753c0a8e0a1
Signed-off-by: Colin Cross <ccross@android.com>
[ARM] l2x0: add declaration for PREFETCH_OFFSET register 2010-04-20T22:20:03+00:00 Gary King gking@nvidia.com 2010-04-20T22:20:03+00:00 eedbc551f9f7e912e8b2bcc08c94bb80e04620b8 Change-Id: I81fe80078a84c872d69f0123bf3bd2cd173fb6b5 
Change-Id: I81fe80078a84c872d69f0123bf3bd2cd173fb6b5
[ARM] gic: add gic_dist_restore, gic_dist_exit routines 2010-04-15T02:59:33+00:00 Gary King gking@nvidia.com 2010-04-15T02:59:33+00:00 6429c4f7e97c7caee15b37c2de1a13b8fde59274 on systems with idle states which power-gate the logic including the gic, such as tegra, the gic distributor needs to be shut down and restored on entry and exit from the architecture idle code Change-Id: I9367ec9866d40757008e1c4b3ef1aba25858bce7 
on systems with idle states which power-gate the logic including
the gic, such as tegra, the gic distributor needs to be shut down
and restored on entry and exit from the architecture idle code

Change-Id: I9367ec9866d40757008e1c4b3ef1aba25858bce7