linux-toradex.git/arch/arm/kernel/entry-armv.S, branch v3.2.20 Linux kernel for Apalis and Colibri modules ARM: 7170/2: fix compilation breakage in entry-armv.S 2011-11-26T21:58:52+00:00 Guennadi Liakhovetski g.liakhovetski@gmx.de 2011-11-22T22:42:12+00:00 c89cefed35c8c5f53f36757f8a6768e390394ee3 Fix compilation failure, when Thumb support is not enabled: arch/arm/kernel/entry-armv.S: Assembler messages: arch/arm/kernel/entry-armv.S:501: Error: backward ref to unknown label "2:" arch/arm/kernel/entry-armv.S:502: Error: backward ref to unknown label "3:" make[2]: *** [arch/arm/kernel/entry-armv.o] Error 1 Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Fix compilation failure, when Thumb support is not enabled:

arch/arm/kernel/entry-armv.S: Assembler messages:
arch/arm/kernel/entry-armv.S:501: Error: backward ref to unknown label "2:"
arch/arm/kernel/entry-armv.S:502: Error: backward ref to unknown label "3:"
make[2]: *** [arch/arm/kernel/entry-armv.o] Error 1

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7031/1: entry: Fix Thumb-2 undef handling for multi-CPU kernels 2011-10-17T08:12:41+00:00 Dave Martin dave.martin@linaro.org 2011-08-19T17:00:08+00:00 ef4c53687e0adf5409896c4fa688b15f8d4dc0c0 When v6 and >=v7 boards are supported in the same kernel, the __und_usr code currently makes a build-time assumption that Thumb-2 instructions occurring in userspace don't need to be supported. Strictly speaking this is incorrect. This patch fixes the above case by doing a run-time check on the CPU architecture in these cases. This only affects kernels which support v6 and >=v7 CPUs together: plain v6 and plain v7 kernels are unaffected. Signed-off-by: Dave Martin <dave.martin@linaro.org> Reviewed-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
When v6 and >=v7 boards are supported in the same kernel, the
__und_usr code currently makes a build-time assumption that Thumb-2
instructions occurring in userspace don't need to be supported.
Strictly speaking this is incorrect.

This patch fixes the above case by doing a run-time check on the
CPU architecture in these cases.  This only affects kernels which
support v6 and >=v7 CPUs together: plain v6 and plain v7 kernels
are unaffected.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Jon Medhurst <tixy@yxit.co.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7030/1: entry: Remove unnecessary masking when decoding Thumb-2 instructions 2011-10-17T08:12:40+00:00 Dave Martin dave.martin@linaro.org 2011-08-19T16:59:27+00:00 85519189df91c8aa9c368de0bdcfd7812200e614 When testing whether a Thumb-2 instruction is 32 bits long or not, the masking done in order to test bits 11-15 of the first instruction halfword won't affect the result of the comparison, so remove it. Signed-off-by: Dave Martin <dave.martin@linaro.org> Reviewed-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
When testing whether a Thumb-2 instruction is 32 bits long or not,
the masking done in order to test bits 11-15 of the first
instruction halfword won't affect the result of the comparison, so
remove it.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Merge branch 'devel-stable' into for-next 2011-07-22T22:09:07+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-07-22T22:09:07+00:00 3ad55155b222f2a901405dea20ff7c68828ecd92 Conflicts: arch/arm/kernel/entry-armv.S 
Conflicts:
	arch/arm/kernel/entry-armv.S
ARM: entry: no need to reload the SPSR value from struct pt_regs 2011-07-02T09:56:12+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-06-26T11:47:08+00:00 30891c90d81133179cc47eb77c30764a3b5dad5c The SVC IRQ, prefetch and data abort handlers preserve the SPSR value via r5 across the exception. Rather than re-loading it from pt_regs, use the preserved value instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The SVC IRQ, prefetch and data abort handlers preserve the SPSR value
via r5 across the exception.  Rather than re-loading it from pt_regs,
use the preserved value instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: entry: data abort: tail-call the main data abort handler 2011-07-02T09:56:11+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-06-26T15:01:26+00:00 da7404725781bc7c736e10cae5521e5604e222a5 Tail-call the main C data abort handler code from the per-CPU helper code. Update the comments in the code wrt the new calling and return register state. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Tail-call the main C data abort handler code from the per-CPU helper
code.  Update the comments in the code wrt the new calling and return
register state.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5 2011-07-02T09:56:11+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-06-26T13:35:07+00:00 3e287bec6fde088bff05ee7f998f53e8ac75b922 Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather than r2/r3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather
than r2/r3.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: entry: prefetch abort: tail-call the main prefetch abort handler 2011-07-02T09:56:10+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-06-26T11:37:35+00:00 8dfe7ac96fedd4f5219879f63a8a546a33609daf Tail-call the main C prefetch abort handler code from the per-CPU helper code. Also note that the helper function becomes ABI compliant in terms of the registers preserved. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Tail-call the main C prefetch abort handler code from the per-CPU
helper code.  Also note that the helper function becomes ABI
compliant in terms of the registers preserved.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: entry: re-allocate registers in irq entry assembly macros 2011-07-02T09:56:10+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-06-26T09:34:02+00:00 d9600c99c549732a501cb727157800623a06175d This avoids the irq entry assembly corrupting r5, thereby allowing it to be preserved through to the svc exit code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
This avoids the irq entry assembly corrupting r5, thereby allowing it
to be preserved through to the svc exit code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: entry: consolidate trace_hardirqs_off into (svc|usr)_entry macros 2011-07-02T09:56:10+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-06-25T16:35:19+00:00 f2741b78b607576f0c256604cb3d9256b3428a32 All handlers now call trace_hardirqs_off, so move this common code into the (svc|usr)_entry assembler macros. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
All handlers now call trace_hardirqs_off, so move this common code into
the (svc|usr)_entry assembler macros.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>