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<title>linux-toradex.git/arch/arm/kernel/head.S, branch v3.0.2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Merge branches 'devel', 'devel-stable' and 'fixes' into for-linus</title>
<updated>2011-05-27T21:59:57+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-05-27T21:59:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=239df0fd5ee25588f8a5ba7f7ee646940cc403f4'/>
<id>239df0fd5ee25588f8a5ba7f7ee646940cc403f4</id>
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<pre>
</pre>
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</entry>
<entry>
<title>ARM: 6942/1: mm: make TTBR1 always point to swapper_pg_dir on ARMv6/7</title>
<updated>2011-05-26T11:14:32+00:00</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2011-05-26T10:22:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d427958a46af24f75d0017c45eadd172273bbf33'/>
<id>d427958a46af24f75d0017c45eadd172273bbf33</id>
<content type='text'>
This patch makes TTBR1 point to swapper_pg_dir so that global, kernel
mappings can be used exclusively on v6 and v7 cores where they are
needed.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
This patch makes TTBR1 point to swapper_pg_dir so that global, kernel
mappings can be used exclusively on v6 and v7 cores where they are
needed.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm/dt: Make __vet_atags also accept a dtb image</title>
<updated>2011-05-11T13:12:32+00:00</updated>
<author>
<name>Grant Likely</name>
<email>grant.likely@secretlab.ca</email>
</author>
<published>2011-04-28T20:27:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4c2896e88d976d0e5b2213c64cde885f5677fa2b'/>
<id>4c2896e88d976d0e5b2213c64cde885f5677fa2b</id>
<content type='text'>
The dtb is passed to the kernel via register r2, which is the same
method that is used to pass an atags pointer.  This patch modifies
__vet_atags to not clear r2 when it encounters a dtb image.

v2: fixed bugs pointed out by Nicolas Pitre

Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
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<pre>
The dtb is passed to the kernel via register r2, which is the same
method that is used to pass an atags pointer.  This patch modifies
__vet_atags to not clear r2 when it encounters a dtb image.

v2: fixed bugs pointed out by Nicolas Pitre

Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'p2v' into devel</title>
<updated>2011-03-16T23:35:27+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-03-16T23:35:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=05e34754518b6a90d5c392790c032575fab12d66'/>
<id>05e34754518b6a90d5c392790c032575fab12d66</id>
<content type='text'>
Conflicts:
	arch/arm/kernel/module.c
	arch/arm/mach-s5pv210/sleep.S
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<pre>
Conflicts:
	arch/arm/kernel/module.c
	arch/arm/mach-s5pv210/sleep.S
</pre>
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</content>
</entry>
<entry>
<title>Merge branch 'misc' into devel</title>
<updated>2011-03-16T23:35:25+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-03-16T23:35:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1f0090a1eaa1b750a2fc5c99c91b790d5322a1fd'/>
<id>1f0090a1eaa1b750a2fc5c99c91b790d5322a1fd</id>
<content type='text'>
Conflicts:
	arch/arm/Kconfig
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<pre>
Conflicts:
	arch/arm/Kconfig
</pre>
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</content>
</entry>
<entry>
<title>ARM: 6747/1: P2V: Thumb2 support</title>
<updated>2011-03-10T16:43:45+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2011-02-21T05:53:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b511d75d6150892e67c8ebfa9dc8eb37ebd02aa3'/>
<id>b511d75d6150892e67c8ebfa9dc8eb37ebd02aa3</id>
<content type='text'>
Adding Thumb2 support to the runtime patching of the virt_to_phys and
phys_to_virt opcodes.

Tested both the 8-bit and the 16-bit fixups, using different placements
in memory to exercize all code paths.

Signed-off-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Reviewed-by: Dave Martin &lt;dave.martin@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Adding Thumb2 support to the runtime patching of the virt_to_phys and
phys_to_virt opcodes.

Tested both the 8-bit and the 16-bit fixups, using different placements
in memory to exercize all code paths.

Signed-off-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Reviewed-by: Dave Martin &lt;dave.martin@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 6648/1: map ATAGs when not in first 1MB of RAM</title>
<updated>2011-02-17T23:27:33+00:00</updated>
<author>
<name>Rob Herring</name>
<email>rob.herring@calxeda.com</email>
</author>
<published>2011-02-02T15:33:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4d901c4271951d110afb13ee9aa73d27a6c8e53d'/>
<id>4d901c4271951d110afb13ee9aa73d27a6c8e53d</id>
<content type='text'>
If ATAGs or DTB pointer is not within first 1MB of RAM, then the boot params
will not be mapped early enough, so map the 1MB region that r2 points to. Only
map the first 1MB when r2 is 0.

Some assembly improvements from Nicolas Pitre.

Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Acked-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
If ATAGs or DTB pointer is not within first 1MB of RAM, then the boot params
will not be mapped early enough, so map the 1MB region that r2 points to. Only
map the first 1MB when r2 is 0.

Some assembly improvements from Nicolas Pitre.

Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Acked-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: P2V: extend to 16-bit translation offsets</title>
<updated>2011-02-17T23:27:33+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-01-04T19:39:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=cada3c0841e1deaec4c0f92654610b028dc683ff'/>
<id>cada3c0841e1deaec4c0f92654610b028dc683ff</id>
<content type='text'>
MSM's memory is aligned to 2MB, which is more than we can do with our
existing method as we're limited to the upper 8 bits.  Extend this by
using two instructions to 16 bits, automatically selected when MSM is
enabled.

Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Reviewed-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Tested-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
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<pre>
MSM's memory is aligned to 2MB, which is more than we can do with our
existing method as we're limited to the upper 8 bits.  Extend this by
using two instructions to 16 bits, automatically selected when MSM is
enabled.

Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Reviewed-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Tested-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: P2V: introduce phys_to_virt/virt_to_phys runtime patching</title>
<updated>2011-02-17T23:27:32+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-01-04T19:09:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=dc21af99fadcfa0ae65b52fd0895f85824f0c288'/>
<id>dc21af99fadcfa0ae65b52fd0895f85824f0c288</id>
<content type='text'>
This idea came from Nicolas, Eric Miao produced an initial version,
which was then rewritten into this.

Patch the physical to virtual translations at runtime.  As we modify
the code, this makes it incompatible with XIP kernels, but allows us
to achieve this with minimal loss of performance.

As many translations are of the form:

	physical = virtual + (PHYS_OFFSET - PAGE_OFFSET)
	virtual = physical - (PHYS_OFFSET - PAGE_OFFSET)

we generate an 'add' instruction for __virt_to_phys(), and a 'sub'
instruction for __phys_to_virt().  We calculate at run time (PHYS_OFFSET
- PAGE_OFFSET) by comparing the address prior to MMU initialization with
where it should be once the MMU has been initialized, and place this
constant into the above add/sub instructions.

Once we have (PHYS_OFFSET - PAGE_OFFSET), we can calculate the real
PHYS_OFFSET as PAGE_OFFSET is a build-time constant, and save this for
the C-mode PHYS_OFFSET variable definition to use.

At present, we are unable to support Realview with Sparsemem enabled
as this uses a complex mapping function, and MSM as this requires a
constant which will not fit in our math instruction.

Add a module version magic string for this feature to prevent
incompatible modules being loaded.

Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Reviewed-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Tested-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This idea came from Nicolas, Eric Miao produced an initial version,
which was then rewritten into this.

Patch the physical to virtual translations at runtime.  As we modify
the code, this makes it incompatible with XIP kernels, but allows us
to achieve this with minimal loss of performance.

As many translations are of the form:

	physical = virtual + (PHYS_OFFSET - PAGE_OFFSET)
	virtual = physical - (PHYS_OFFSET - PAGE_OFFSET)

we generate an 'add' instruction for __virt_to_phys(), and a 'sub'
instruction for __phys_to_virt().  We calculate at run time (PHYS_OFFSET
- PAGE_OFFSET) by comparing the address prior to MMU initialization with
where it should be once the MMU has been initialized, and place this
constant into the above add/sub instructions.

Once we have (PHYS_OFFSET - PAGE_OFFSET), we can calculate the real
PHYS_OFFSET as PAGE_OFFSET is a build-time constant, and save this for
the C-mode PHYS_OFFSET variable definition to use.

At present, we are unable to support Realview with Sparsemem enabled
as this uses a complex mapping function, and MSM as this requires a
constant which will not fit in our math instruction.

Add a module version magic string for this feature to prevent
incompatible modules being loaded.

Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Reviewed-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Tested-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: P2V: eliminate head.S use of PHYS_OFFSET for !XIP_KERNEL</title>
<updated>2011-02-17T23:27:30+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-01-04T19:04:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=72a20e22f49e2dad3180c23980a9df1c63faab0a'/>
<id>72a20e22f49e2dad3180c23980a9df1c63faab0a</id>
<content type='text'>
head.S makes use of PHYS_OFFSET.  When it becomes a variable, the
assembler won't understand this.  Compute PHYS_OFFSET by the following
method.  This code is linked at its virtual address, but run at before
the MMU is enabled, so at his physical address.

1:	.long	.
	.long	PAGE_OFFSET

	adr	r0, 1b		@ r0 = physical ','
	ldmia	r0, {r1, r2}	@ r1 = virtual '.', r2 = PAGE_OFFSET
	sub	r1, r0, r1	@ r1 = physical-virtual
	add	r2, r2, r1	@ r2 = PAGE_OFFSET + physical-virtual
				@    := PHYS_OFFSET.

Switch XIP users of PHYS_OFFSET to use PLAT_PHYS_OFFSET - we can't
use this method for XIP kernels as the code doesn't execute in RAM.

Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Reviewed-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
head.S makes use of PHYS_OFFSET.  When it becomes a variable, the
assembler won't understand this.  Compute PHYS_OFFSET by the following
method.  This code is linked at its virtual address, but run at before
the MMU is enabled, so at his physical address.

1:	.long	.
	.long	PAGE_OFFSET

	adr	r0, 1b		@ r0 = physical ','
	ldmia	r0, {r1, r2}	@ r1 = virtual '.', r2 = PAGE_OFFSET
	sub	r1, r0, r1	@ r1 = physical-virtual
	add	r2, r2, r1	@ r2 = PAGE_OFFSET + physical-virtual
				@    := PHYS_OFFSET.

Switch XIP users of PHYS_OFFSET to use PLAT_PHYS_OFFSET - we can't
use this method for XIP kernels as the code doesn't execute in RAM.

Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Reviewed-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
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