linux-toradex.git/arch/arm/kernel/perf_event_xscale.c, branch v3.4.18

ARM: 7357/1: perf: fix overflow handling for xscale2 PMUs

2012-03-07T09:40:49+00:00

xscale2 PMUs indicate overflow not via the PMU control register, but by
a separate overflow FLAG register instead.

This patch fixes the xscale2 PMU code to use this register to detect
to overflow and ensures that we clear any pending overflow when
disabling a counter.

Cc: 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7356/1: perf: check that we have an event in the PMU IRQ handlers

2012-03-07T09:40:49+00:00

The PMU IRQ handlers in perf assume that if a counter has overflowed
then perf must be responsible. In the paranoid world of crazy hardware,
this could be false, so check that we do have a valid event before
attempting to dereference NULL in the interrupt path.

Cc: 
Signed-off-by: Ming Lei 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7354/1: perf: limit sample_period to half max_period in non-sampling mode

2012-03-07T09:40:48+00:00

On ARM, the PMU does not stop counting after an overflow and therefore
IRQ latency affects the new counter value read by the kernel. This is
significant for non-sampling runs where it is possible for the new value
to overtake the previous one, causing the delta to be out by up to
max_period events.

Commit a737823d ("ARM: 6835/1: perf: ensure overflows aren't missed due
to IRQ latency") attempted to fix this problem by allowing interrupt
handlers to pass an overflow flag to the event update function, causing
the overflow calculation to assume that the counter passed through zero
when going from prev to new. Unfortunately, this doesn't work when
overflow occurs on the perf_task_tick path because we have the flag
cleared and end up computing a large negative delta.

This patch removes the overflow flag from armpmu_event_update and
instead limits the sample_period to half of the max_period for
non-sampling profiling runs.

Cc: 
Signed-off-by: Ming Lei 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: perf: add support for stalled cycle ABI events

2011-12-02T15:16:16+00:00

Commit 8f622422 ("perf events: Add generic front-end and back-end
stalled cycle event definitions") added two new ABI events for counting
stalled cycles.

This patch adds support for these new events to the ARM perf
implementation.

Cc: Jamie Iles 
Cc: Jean Pihet 
Signed-off-by: Will Deacon

ARM: perf: remove cpu-related misnomers

2011-08-31T09:50:12+00:00

Currently struct cpu_hw_events stores data on events running on a
PMU associated with a CPU. As this data is general enough to be used
for system PMUs, this name is a misnomer, and may cause confusion when
it is used for system PMUs.

Additionally, 'armpmu' is commonly used as a parameter name for an
instance of struct arm_pmu. The name is also used for a global instance
which represents the CPU's PMU.

As cpu_hw_events is now not tied to CPU PMUs, it is renamed to
pmu_hw_events, with instances of it renamed similarly. As the global
'armpmu' is CPU-specfic, it is renamed to cpu_pmu. This should make it
clearer which code is generic, and which is coupled with the CPU.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: refactor event mapping

2011-08-31T09:50:09+00:00

Currently mapping an event type to a hardware configuration value
depends on the data being pointed to from struct arm_pmu. These fields
(cache_map, event_map, raw_event_mask) are currently specific to CPU
PMUs, and do not serve the general case well.

This patch replaces the event map pointers on struct arm_pmu with a new
'map_event' function pointer. Small shim functions are used to reuse
the existing common code.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: lock PMU registers per-CPU

2011-08-31T09:50:07+00:00

Currently, a single lock serialises access to CPU PMU registers. This
global locking is unnecessary as PMU registers are local to the CPU
they monitor.

This patch replaces the global lock with a per-CPU lock. As the lock is
in struct cpu_hw_events, PMUs providing a single cpu_hw_events instance
can be locked globally.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: remove active_mask

2011-08-31T09:50:02+00:00

Currently, pmu_hw_events::active_mask is used to keep track of which
events are active in hardware. As we can stop counters and their
interrupts, this is unnecessary.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: index Xscale and ARMv6 event counters starting from zero

2011-08-31T09:18:00+00:00

Now that the ARMv7 PMU backend indexes event counters from zero, follow
suit and do the same for ARMv6 and Xscale.

Acked-by: Jamie Iles 
Reviewed-by: Jean Pihet 
Signed-off-by: Mark Rutland 
Signed-off-by: Will Deacon

ARM: perf: de-const struct arm_pmu

2011-08-31T09:16:58+00:00

This patch removes const qualifiers from instances of struct arm_pmu,
and functions initialising them, in preparation for generalising
arm_pmu usage to system (AKA uncore) PMUs.

This will allow for dynamically modifiable structures (locks,
struct pmu) to be added as members of struct arm_pmu.

Acked-by: Jamie Iles 
Reviewed-by: Jean Pihet 
Signed-off-by: Mark Rutland 
Signed-off-by: Will Deacon