linux-toradex.git/arch/arm/kernel/smp_twd.c, branch v3.4.18 Linux kernel for Apalis and Colibri modules Revert "ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpus" 2012-04-19T18:35:10+00:00 Russell King rmk+kernel@arm.linux.org.uk 2012-04-19T18:35:10+00:00 3cd88f993e8b24855ed135b36bc6ed53dff38f08 This reverts commit 9f85550347f51c79a917b2aec04c90691c11e20a. Peter Zijlstra says: | Argh, how did that ever make it upstream, please drop. | | Russell, please make that go away upstream. | | Like I said, this is both completely the wrong way to solve, and you're | so not paying attention, see: | | 5fbd036b552f633abb394a319f7c62a5c86a9cd7 | 2baab4e90495ebc9826c93f79d74d6e60a828d24 | e3831edd59edf57ca11fc289f08961b20baf5146 | | What's even worse: | | git describe --contains 9f85550347f51c79a917b2aec04c90691c11e20a --match "v*" | v3.4-rc3~1^2~3 | | that nonsense got merged long after those other commits. Linus Walleij says: | My bad, was because the initial patch was submitted march 9th before | these fixes were merged: | http://marc.info/?l=linux-arm-kernel&m=133159655513844&w=2 | | It was pending for a while in Russell's patch tracker and I | rebased it to -rc2 without paying enough attention to recent | related scheduler fixes ... lesson learned. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
This reverts commit 9f85550347f51c79a917b2aec04c90691c11e20a.

Peter Zijlstra says:
| Argh, how did that ever make it upstream, please drop.
|
| Russell, please make that go away upstream.
|
| Like I said, this is both completely the wrong way to solve, and you're
| so not paying attention, see:
|
|   5fbd036b552f633abb394a319f7c62a5c86a9cd7
|   2baab4e90495ebc9826c93f79d74d6e60a828d24
|   e3831edd59edf57ca11fc289f08961b20baf5146
|
| What's even worse:
|
| git describe --contains 9f85550347f51c79a917b2aec04c90691c11e20a --match "v*"
| v3.4-rc3~1^2~3
|
| that nonsense got merged long after those other commits.

Linus Walleij says:
| My bad, was because the initial patch was submitted march 9th before
| these fixes were merged:
| http://marc.info/?l=linux-arm-kernel&m=133159655513844&w=2
|
| It was pending for a while in Russell's patch tracker and I
| rebased it to -rc2 without paying enough attention to recent
| related scheduler fixes ... lesson learned.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpus 2012-04-15T21:00:29+00:00 Linus Walleij linus.walleij@linaro.org 2012-04-10T11:37:42+00:00 9f85550347f51c79a917b2aec04c90691c11e20a During booting of cpu1, there is a short window where cpu1 is online, but not active where cpu1 is occupied by waiting to become active. If cpu0 then decides to schedule something on cpu1 and wait for it to complete, before cpu0 has set cpu1 active, we have a deadlock. Typically it's this CPU frequency transition that happens at this time, so let's just not wait for it to happen, it will happen whenever the CPU eventually comes online instead. Cc: Peter Zijlstra <peterz@infradead.org> Cc: stable@kernel.org Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Reviewed-by: Rickard Andersson <rickard.andersson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
During booting of cpu1, there is a short window where cpu1
is online, but not active where cpu1 is occupied by waiting
to become active. If cpu0 then decides to schedule something
on cpu1 and wait for it to complete, before cpu0 has set
cpu1 active, we have a deadlock.

Typically it's this CPU frequency transition that happens at
this time, so let's just not wait for it to happen, it will
happen whenever the CPU eventually comes online instead.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: stable@kernel.org
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-by: Rickard Andersson <rickard.andersson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Merge branch 'renesas/timer' into next/timer 2012-03-20T09:41:43+00:00 Arnd Bergmann arnd@arndb.de 2012-03-19T20:46:32+00:00 b2f1df8d2fc14bf7e6d9d967043d4b60c2efd8dc Conflicts: arch/arm/mach-shmobile/timer.c This resolves a nonobvious merge conflict between renesas timer changes in the global timer changes with those from the renesas soc branch and last minute bug fixes that went into v3.3. Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
Conflicts:
	arch/arm/mach-shmobile/timer.c

This resolves a nonobvious merge conflict between renesas
timer changes in the global timer changes with those
from the renesas soc branch and last minute bug fixes that
went into v3.3.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM: smp_twd: remove old local timer interface 2012-03-13T13:45:54+00:00 Marc Zyngier marc.zyngier@arm.com 2012-01-10T23:00:54+00:00 9248510469b46bc17b90cf62cb8d9e7c9a5f9965 Now that all users of the previous local timer interface have been converted to the runtime registration API, make this interface the only one supported for this driver. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
Now that all users of the previous local timer interface
have been converted to the runtime registration API, make
this interface the only one supported for this driver.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: smp_twd: add device tree support 2012-03-13T13:27:51+00:00 Marc Zyngier marc.zyngier@arm.com 2012-01-10T22:15:45+00:00 d8e0364364d333feb4564bb7d7d983182b34427e Add bindings to support DT discovery of the ARM Timer Watchdog (aka TWD). Only the timer side is converted by this patch. Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
Add bindings to support DT discovery of the ARM Timer Watchdog
(aka TWD). Only the timer side is converted by this patch.

Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: smp_twd: add runtime registration support 2012-03-13T13:27:50+00:00 Marc Zyngier marc.zyngier@arm.com 2012-01-10T19:39:26+00:00 81e46f7b6dcec485bcb1f988ba4dc5b20189573c Add support for the new registration interface to smp_twd. Platforms can populate a struct twd_local_timer with MMIO and IRQ resources, and then call twd_local_timer_register() to have the timer registered with the core. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
Add support for the new registration interface to smp_twd.
Platforms can populate a struct twd_local_timer with MMIO
and IRQ resources, and then call twd_local_timer_register()
to have the timer registered with the core.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: smp_twd: make local_timer_stop a symbol instead of a #define 2012-03-13T13:27:49+00:00 Marc Zyngier marc.zyngier@arm.com 2012-01-10T19:07:28+00:00 abde710ca8776f851e41c3dfe78ad7dcafa26dc9 When CONFIG_HAVE_ARM_TWD is selected, local_timer_stop is a #define, while all other local timers are using a real function. Convert it to an alias of twd_timer_stop, as it helps converting all local timers to another internal API in a sane way. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
When CONFIG_HAVE_ARM_TWD is selected, local_timer_stop is a #define,
while all other local timers are using a real function.

Convert it to an alias of twd_timer_stop, as it helps converting
all local timers to another internal API in a sane way.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: 7336/1: smp_twd: Don't register CPUFREQ notifiers if local timers are not initialised 2012-02-21T09:26:46+00:00 Santosh Shilimkar santosh.shilimkar@ti.com 2012-02-21T09:24:22+00:00 910ba598c818243cf3de2f97e03c49948bbb0511 Current ARM local timer code registers CPUFREQ notifiers even in case the twd_timer_setup() isn't called. That seems to be wrong and would eventually lead to kernel crash on the CPU frequency transitions on the SOCs where the local timer doesn't exist or broken because of hardware BUG. Fix it by testing twd_evt and *__this_cpu_ptr(twd_evt). The issue was observed with v3.3-rc3 and building an OMAP2+ kernel on OMAP3 SOC which doesn't have TWD. Below is the dump for reference : Unable to handle kernel paging request at virtual address 007e900 pgd = cdc20000 [007e9000] *pgd=00000000 Internal error: Oops: 5 [#1] SMP Modules linked in: CPU: 0 Not tainted (3.3.0-rc3-pm+debug+initramfs #9) PC is at twd_update_frequency+0x34/0x48 LR is at twd_update_frequency+0x10/0x48 pc : [<c001382c>] lr : [<c0013808>] psr: 60000093 sp : ce311dd8 ip : 00000000 fp : 00000000 r10: 00000000 r9 : 00000001 r8 : ce310000 r7 : c0440458 r6 : c00137f8 r5 : 00000000 r4 : c0947a74 r3 : 00000000 r2 : 007e9000 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment usr Control: 10c5387d Table: 8dc20019 DAC: 00000015 Process sh (pid: 599, stack limit = 0xce3102f8) Stack: (0xce311dd8 to 0xce312000) 1dc0: 6000c 1de0: 00000001 00000002 00000000 00000000 00000000 00000000 00000 1e00: ffffffff c093d8f0 00000000 ce311ebc 00000001 00000001 ce310 1e20: c001386c c0437c4c c0e95b60 c0e95ba8 00000001 c0e95bf8 ffff4 1e40: 00000000 00000000 c005ef74 ce310000 c0435cf0 ce311ebc 00000 1e60: ce352b40 0007a120 c08d5108 c08ba040 c08ba040 c005f030 00000 1e80: c08bc554 c032fe2c 0007a120 c08d4b64 ce352b40 c08d8618 ffff8 1ea0: c08ba040 c033364c ce311ecc c0433b50 00000002 ffffffea c0330 1ec0: 0007a120 0007a120 22222201 00000000 22222222 00000000 ce357 1ee0: ce3d6000 cdc2aed8 ce352ba0 c0470164 00000002 c032f47c 00034 1f00: c0331cac ce352b40 00000007 c032f6d0 ce352bbc 0003d090 c0930 1f20: c093d8bc c03306a4 00000007 ce311f80 00000007 cdc2aec0 ce358 1f40: ce8d20c0 00000007 b6fe5000 ce311f80 00000007 ce310000 0000c 1f60: c000de74 ce987400 ce8d20c0 b6fe5000 00000000 00000000 0000c 1f80: 00000000 00000000 001fbac8 00000000 00000007 001fbac8 00004 1fa0: c000df04 c000dd60 00000007 001fbac8 00000001 b6fe5000 00000 1fc0: 00000007 001fbac8 00000007 00000004 b6fe5000 00000000 00202 1fe0: 00000000 beb565f8 00101ffc 00008e8c 60000010 00000001 00000 [<c001382c>] (twd_update_frequency+0x34/0x48) from [<c008ac4c>] ) [<c008ac4c>] (smp_call_function_single+0x17c/0x1c8) from [<c0013) [<c0013890>] (twd_cpufreq_transition+0x24/0x30) from [<c0437c4c>) [<c0437c4c>] (notifier_call_chain+0x44/0x84) from [<c005efe4>] () [<c005efe4>] (__srcu_notifier_call_chain+0x70/0xa4) from [<c005f) [<c005f030>] (srcu_notifier_call_chain+0x18/0x20) from [<c032fe2) [<c032fe2c>] (cpufreq_notify_transition+0xc8/0x1b0) from [<c0333) [<c033364c>] (omap_target+0x1b4/0x28c) from [<c032f47c>] (__cpuf) [<c032f47c>] (__cpufreq_driver_target+0x50/0x64) from [<c0331d24) [<c0331d24>] (cpufreq_set+0x78/0x98) from [<c032f6d0>] (store_sc) [<c032f6d0>] (store_scaling_setspeed+0x5c/0x74) from [<c03306a4>) [<c03306a4>] (store+0x58/0x74) from [<c014d868>] (sysfs_write_fi) [<c014d868>] (sysfs_write_file+0x80/0xb4) from [<c00f2c2c>] (vfs) [<c00f2c2c>] (vfs_write+0xa8/0x138) from [<c00f2e9c>] (sys_write) [<c00f2e9c>] (sys_write+0x40/0x6c) from [<c000dd60>] (ret_fast_s) Code: e594300c e792210c e1a01000 e5840004 (e7930002) ---[ end trace 5da3b5167c1ecdda ]--- Reported-by: Kevin Hilman <khilman@ti.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Current ARM local timer code registers CPUFREQ notifiers even in case
the twd_timer_setup() isn't called. That seems to be wrong and
would eventually lead to kernel crash on the CPU frequency transitions
on the SOCs where the local timer doesn't exist or broken because of
hardware BUG. Fix it by testing twd_evt and *__this_cpu_ptr(twd_evt).

The issue was observed with v3.3-rc3 and building an OMAP2+ kernel
on OMAP3 SOC which doesn't have TWD.

Below is the dump for reference :

 Unable to handle kernel paging request at virtual address 007e900
 pgd = cdc20000
 [007e9000] *pgd=00000000
 Internal error: Oops: 5 [#1] SMP
 Modules linked in:
 CPU: 0    Not tainted  (3.3.0-rc3-pm+debug+initramfs #9)
 PC is at twd_update_frequency+0x34/0x48
 LR is at twd_update_frequency+0x10/0x48
 pc : [<c001382c>]    lr : [<c0013808>]    psr: 60000093
 sp : ce311dd8  ip : 00000000  fp : 00000000
 r10: 00000000  r9 : 00000001  r8 : ce310000
 r7 : c0440458  r6 : c00137f8  r5 : 00000000  r4 : c0947a74
 r3 : 00000000  r2 : 007e9000  r1 : 00000000  r0 : 00000000
 Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment usr
 Control: 10c5387d  Table: 8dc20019  DAC: 00000015
 Process sh (pid: 599, stack limit = 0xce3102f8)
 Stack: (0xce311dd8 to 0xce312000)
 1dc0:                                                       6000c
 1de0: 00000001 00000002 00000000 00000000 00000000 00000000 00000
 1e00: ffffffff c093d8f0 00000000 ce311ebc 00000001 00000001 ce310
 1e20: c001386c c0437c4c c0e95b60 c0e95ba8 00000001 c0e95bf8 ffff4
 1e40: 00000000 00000000 c005ef74 ce310000 c0435cf0 ce311ebc 00000
 1e60: ce352b40 0007a120 c08d5108 c08ba040 c08ba040 c005f030 00000
 1e80: c08bc554 c032fe2c 0007a120 c08d4b64 ce352b40 c08d8618 ffff8
 1ea0: c08ba040 c033364c ce311ecc c0433b50 00000002 ffffffea c0330
 1ec0: 0007a120 0007a120 22222201 00000000 22222222 00000000 ce357
 1ee0: ce3d6000 cdc2aed8 ce352ba0 c0470164 00000002 c032f47c 00034
 1f00: c0331cac ce352b40 00000007 c032f6d0 ce352bbc 0003d090 c0930
 1f20: c093d8bc c03306a4 00000007 ce311f80 00000007 cdc2aec0 ce358
 1f40: ce8d20c0 00000007 b6fe5000 ce311f80 00000007 ce310000 0000c
 1f60: c000de74 ce987400 ce8d20c0 b6fe5000 00000000 00000000 0000c
 1f80: 00000000 00000000 001fbac8 00000000 00000007 001fbac8 00004
 1fa0: c000df04 c000dd60 00000007 001fbac8 00000001 b6fe5000 00000
 1fc0: 00000007 001fbac8 00000007 00000004 b6fe5000 00000000 00202
 1fe0: 00000000 beb565f8 00101ffc 00008e8c 60000010 00000001 00000
 [<c001382c>] (twd_update_frequency+0x34/0x48) from [<c008ac4c>] )
 [<c008ac4c>] (smp_call_function_single+0x17c/0x1c8) from [<c0013)
 [<c0013890>] (twd_cpufreq_transition+0x24/0x30) from [<c0437c4c>)
 [<c0437c4c>] (notifier_call_chain+0x44/0x84) from [<c005efe4>] ()
 [<c005efe4>] (__srcu_notifier_call_chain+0x70/0xa4) from [<c005f)
 [<c005f030>] (srcu_notifier_call_chain+0x18/0x20) from [<c032fe2)
 [<c032fe2c>] (cpufreq_notify_transition+0xc8/0x1b0) from [<c0333)
 [<c033364c>] (omap_target+0x1b4/0x28c) from [<c032f47c>] (__cpuf)
 [<c032f47c>] (__cpufreq_driver_target+0x50/0x64) from [<c0331d24)
 [<c0331d24>] (cpufreq_set+0x78/0x98) from [<c032f6d0>] (store_sc)
 [<c032f6d0>] (store_scaling_setspeed+0x5c/0x74) from [<c03306a4>)
 [<c03306a4>] (store+0x58/0x74) from [<c014d868>] (sysfs_write_fi)
 [<c014d868>] (sysfs_write_file+0x80/0xb4) from [<c00f2c2c>] (vfs)
 [<c00f2c2c>] (vfs_write+0xa8/0x138) from [<c00f2e9c>] (sys_write)
 [<c00f2e9c>] (sys_write+0x40/0x6c) from [<c000dd60>] (ret_fast_s)
 Code: e594300c e792210c e1a01000 e5840004 (e7930002)
 ---[ end trace 5da3b5167c1ecdda ]---

Reported-by: Kevin Hilman <khilman@ti.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7297/1: smp_twd: make sure timer is stopped before registering it 2012-01-23T10:20:07+00:00 Marc Zyngier Marc.Zyngier@arm.com 2012-01-20T11:24:47+00:00 c214455f3205fa20819da6d67a8b20609ff786e7 On secondary CPUs, the Timer Control Register is not reset to a sane value before the timer is registered, and the TRM doesn't seem to indicate any reset value either. In some cases, the kernel will take an interrupt too early, depending on what junk was present in the registers at reset time. The fix is to set the Timer Control Register to 0 before registering the clock_event_device and enabling the interrupt. Problem seen on VE (Cortex A5) and Tegra. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
On secondary CPUs, the Timer Control Register is not reset
to a sane value before the timer is registered, and the TRM
doesn't seem to indicate any reset value either. In some cases,
the kernel will take an interrupt too early, depending on what
junk was present in the registers at reset time.

The fix is to set the Timer Control Register to 0 before
registering the clock_event_device and enabling the interrupt.

Problem seen on VE (Cortex A5) and Tegra.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7212/1: smp_twd: reconfigure clockevents after cpufreq change 2011-12-23T22:54:50+00:00 Linus Walleij linus.walleij@linaro.org 2011-12-13T11:48:18+00:00 4fd7f9b128107034fa925b6877fae3c275f0da86 This break-out from Colin Cross' cpufreq-aware TWD patch will handle the case when our localtimer's clock changes with the cpu clock. A cpufreq transtion notifier will be registered only if the platform has supplied a specified clock to the TWD. After a cpufreq transition, update the clockevent's frequency by fetching the new clock rate from the clock framework and reprogram the next clock event. The necessary changes in the clockevents framework was done by Thomas Gleixner in kernel v3.0. ChangeLog v1->v2: - Replace IS_ERR_OR_NULL() with IS_ERR() in twd_clk check. - Update code to use the already existing per-cpu array of TWD clockevents instead of adding cruft. [Broke out, ifdef:ed CPUfreq stuff for non-cpufreq configs] [Rebased to newer TWD base with per-CPU clock array] Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
This break-out from Colin Cross' cpufreq-aware TWD patch
will handle the case when our localtimer's clock changes with
the cpu clock. A cpufreq transtion notifier will be registered
only if the platform has supplied a specified clock to the TWD.

After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.

The necessary changes in the clockevents framework was done by
Thomas Gleixner in kernel v3.0.

ChangeLog v1->v2:
- Replace IS_ERR_OR_NULL() with IS_ERR() in twd_clk check.
- Update code to use the already existing per-cpu array of TWD
  clockevents instead of adding cruft.

[Broke out, ifdef:ed CPUfreq stuff for non-cpufreq configs]
[Rebased to newer TWD base with per-CPU clock array]

Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>