This avoids races in the VFP code where the dead thread may have
state on another CPU.  By moving this code to exit_thread(), we
will be running as the thread, and therefore be running on the
current CPU.

This means that we can ensure that the only local state is accessed
in the thread notifiers.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Change-Id: I195ea8ce8f5f438166b402411eaff3f33f4b2490
Reviewed-on: http://git-master/r/2731
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

We can't be holding the mmap_sem while calling flush_cache_user_range
because the flush can fault. If we fault on a user address, the
page fault handler will try to take mmap_sem again. Since both places
acquire the read lock, most of the time it succeeds. However, if another
thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in
between the call to flush_cache_user_range and the fault, the down_read
in do_page_fault will deadlock.

Also, since we really can't be holding the mmap_sem while calling
flush_cache_user_range AND vma is actually unused by the flush itself,
get rid of vma as an argument.

Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106
Signed-off-by: Dima Zavin <dima@android.com>

tegra 2 systems have a hardware errata which causes bit 20 of the
TLS register (CP15 c13, operations 2-4) to be unreliable.

in common user space threading libraries (glibc pthreads, bionic
pthreads), the value stored in this register is guaranteed to be
at least word-aligned, leaving bit 0 free.

the work-around for this hardware errata is storing bit 20 of the
user space-provided TLS value into bit 0 of the register inside
__set_tls, and restoring it in the get_tls helper.

This reverts commit 197d3f06e732a0428701c4f3550b91f9fc1297ab.

the local timers support prescaling the event timeout, which
can be used to efficiently update the countdown frequency to
compensate for CPU frequency changes.

Change-Id: Ic4d0236f39fe1b8c6d436625bf9b584c417f6f00

add ARCH_HAS_CPU_IDLE_WAIT and ARCH_HAS_DEFAULT_IDLE configuration,
and expose default_idle and cpu_idle_wait

cpu_idle_wait implementation based on the implementation in the x86 tree

Change-Id: Ie24b6336db833cc638868abfdba822889646d0a8
Reviewed-on: http://git-master/r/950
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

when ARM MP processors (MPCore, CortexA9MP) enter or exit coherency, the
tags stored by the snoop control unit for the processor should be invalidated
to prevent snooping of incorrect cache lines.

Change-Id: I87f6293c26fcbd686dbfbed6b84a8df5e5fe6f24

Since this IRQ descriptor doesn't have an action registered, it is
allowed for probing via probe_irq_on/off() and it will be disabled by
the latter function. This patch sets the IRQ_NOPROBE status bit for the
local timer descriptor.

Signed-off-by: Varun Swara <Varun.Swara@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The page table and secondary data which we're asking the secondary CPU
to make use of has to hit RAM to ensure that the secondary CPU can see
it since it may not be taking part in coherency or cache searches at
this point.

Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>