linux-toradex.git/arch/arm/kvm/interrupts_head.S, branch v4.4.95

arm: KVM: Disable virtual timer even if the guest is not using it

2015-09-17T12:11:48+00:00

When running a guest with the architected timer disabled (with QEMU and
the kernel_irqchip=off option, for example), it is important to make
sure the timer gets turned off. Otherwise, the guest may try to
enable it anyway, leading to a screaming HW interrupt.

The fix is to unconditionally turn off the virtual timer on guest
exit.

Cc: stable@vger.kernel.org
Signed-off-by: Marc Zyngier

arm/arm64: KVM: vgic: Do not save GICH_HCR / ICH_HCR_EL2

2015-06-17T08:59:55+00:00

The GIC Hypervisor Configuration Register is used to enable
the delivery of virtual interupts to a guest, as well as to
define in which conditions maintenance interrupts are delivered
to the host.

This register doesn't contain any information that we need to
read back (the EOIcount is utterly useless for us).

So let's save ourselves some cycles, and not save it before
writing zero to it.

Signed-off-by: Marc Zyngier

arm: KVM: force execution of HCPTR access on VM exit

2015-06-17T08:40:14+00:00

On VM entry, we disable access to the VFP registers in order to
perform a lazy save/restore of these registers.

On VM exit, we restore access, test if we did enable them before,
and save/restore the guest/host registers if necessary. In this
sequence, the FPEXC register is always accessed, irrespective
of the trapping configuration.

If the guest didn't touch the VFP registers, then the HCPTR access
has now enabled such access, but we're missing a barrier to ensure
architectural execution of the new HCPTR configuration. If the HCPTR
access has been delayed/reordered, the subsequent access to FPEXC
will cause a trap, which we aren't prepared to handle at all.

The same condition exists when trapping to enable VFP for the guest.

The fix is to introduce a barrier after enabling VFP access. In the
vmexit case, it can be relaxed to only takes place if the guest hasn't
accessed its view of the VFP registers, making the access to FPEXC safe.

The set_hcptr macro is modified to deal with both vmenter/vmexit and
vmtrap operations, and now takes an optional label that is branched to
when the guest hasn't touched the VFP registers.

Reported-by: Vikram Sethi 
Cc: stable@kernel.org	# v3.9+
Signed-off-by: Marc Zyngier

arm/arm64: KVM: Kill CONFIG_KVM_ARM_{VGIC,TIMER}

2015-03-12T14:15:27+00:00

We can definitely decide at run-time whether to use the GIC and timers
or not, and the extra code and data structures that we allocate space
for is really negligable with this config option, so I don't think it's
worth the extra complexity of always having to define stub static
inlines.  The !CONFIG_KVM_ARM_VGIC/TIMER case is pretty much an untested
code path anyway, so we're better off just getting rid of it.

Signed-off-by: Christoffer Dall 
Acked-by: Marc Zyngier

arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs

2014-10-16T08:57:41+00:00

The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
store these as an array of two such registers on the vgic vcpu struct.
However, we access them as a single 64-bit value or as a bitmap pointer
in the generic vgic code, which breaks BE support.

Instead, store them as u64 values on the vgic structure and do the
word-swapping in the assembly code, which already handles the byte order
for BE systems.

Tested-by: Victor Kamensky 
Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

ARM: KVM: handle 64bit values passed to mrcc or from mcrr instructions in BE case

2014-07-11T11:57:38+00:00

In some cases the mcrr and mrrc instructions in combination with the ldrd
and strd instructions need to deal with 64bit value in memory. The ldrd
and strd instructions already handle endianness within word (register)
boundaries but to get effect of the whole 64bit value represented correctly,
rr_lo_hi macro is introduced and is used to swap registers positions when
the mcrr and mrrc instructions are used. That has the effect of swapping
two words.

Signed-off-by: Victor Kamensky 
Reviewed-by: Christoffer Dall 
Acked-by: Marc Zyngier 
Signed-off-by: Marc Zyngier

ARM: KVM: fix vgic V7 assembler code to work in BE image

2014-07-11T11:57:38+00:00

The vgic h/w registers are little endian; when BE asm code
reads/writes from/to them, it needs to do byteswap after/before.
Byteswap code uses ARM_BE8 wrapper to add swap only if
CONFIG_CPU_BIG_ENDIAN is configured.

Signed-off-by: Victor Kamensky 
Reviewed-by: Christoffer Dall 
Acked-by: Marc Zyngier 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: vgic: move GICv2 registers to their own structure

2014-07-11T11:57:31+00:00

In order to make way for the GICv3 registers, move the v2-specific
registers to their own structure.

Acked-by: Catalin Marinas 
Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

ARM: KVM: add world-switch for AMAIR{0,1}

2014-03-03T01:15:24+00:00

HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
In order to minimise the amount of surprise a guest could generate by
trying to access these registers with caches off, add them to the
list of registers we switch/handle.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Acked-by: Catalin Marinas

ARM: KVM: introduce per-vcpu HYP Configuration Register

2014-03-03T01:15:23+00:00

So far, KVM/ARM used a fixed HCR configuration per guest, except for
the VI/VF/VA bits to control the interrupt in absence of VGIC.

With the upcoming need to dynamically reconfigure trapping, it becomes
necessary to allow the HCR to be changed on a per-vcpu basis.

The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR
field, initialized at setup time.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Acked-by: Catalin Marinas