linux-toradex.git/arch/arm/lib/bitops.h, branch v4.10

Revert "arm: move exports to definitions"

2016-11-23T10:00:03+00:00

This reverts commit 4dd1837d7589f468ed109556513f476e7a7f9121.

Moving the exports for assembly code into the assembly files breaks
KSYM trimming, but also breaks modversions.

While fixing the KSYM trimming is trivial, fixing modversions brings
us to a technically worse position that we had prior to the above
change:

- We end up with the prototype definitions divorsed from everything
  else, which means that adding or removing assembly level ksyms
  become more fragile:
  * if adding a new assembly ksyms export, a missed prototype in
    asm-prototypes.h results in a successful build if no module in
    the selected configuration makes use of the symbol.
  * when removing a ksyms export, asm-prototypes.h will get forgotten,
    with armksyms.c, you'll get a build error if you forget to touch
    the file.

- We end up with the same amount of include files and prototypes,
  they're just in a header file instead of a .c file with their
  exports.

As for lines of code, we don't get much of a size reduction:
 (original commit)
 47 files changed, 131 insertions(+), 208 deletions(-)
 (fix for ksyms trimming)
 7 files changed, 18 insertions(+), 5 deletions(-)
 (two fixes for modversions)
 1 file changed, 34 insertions(+)
 3 files changed, 7 insertions(+), 2 deletions(-)
which results in a net total of only 25 lines deleted.

As there does not seem to be much benefit from this change of approach,
revert the change.

Signed-off-by: Russell King

arm: move exports to definitions

2016-08-08T03:47:21+00:00

Signed-off-by: Al Viro

ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+

2014-07-18T11:29:04+00:00

ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls.  Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).

We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.

Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code.  This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.

Reported-by: Will Deacon 
Tested-by: Stephen Warren  # Tegra Jetson TK1
Tested-by: Robert Jarzmik  # mioa701_bootresume.S
Tested-by: Andrew Lunn  # Kirkwood
Tested-by: Shawn Guo 
Tested-by: Tony Lindgren  # OMAPs
Tested-by: Gregory CLEMENT  # Armada XP, 375, 385
Acked-by: Sekhar Nori  # DaVinci
Acked-by: Christoffer Dall  # kvm/hyp
Acked-by: Haojian Zhuang  # PXA3xx
Acked-by: Stefano Stabellini  # Xen
Tested-by: Uwe Kleine-König  # ARMv7M
Tested-by: Simon Horman  # Shmobile
Signed-off-by: Russell King

ARM: 7984/1: prefetch: add prefetchw invocations for barriered atomics

2014-02-25T11:30:20+00:00

After a bunch of benchmarking on the interaction between dmb and pldw,
it turns out that issuing the pldw *after* the dmb instruction can
give modest performance gains (~3% atomic_add_return improvement on a
dual A15).

This patch adds prefetchw invocations to our barriered atomic operations
including cmpxchg, test_and_xxx and futexes.

Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7893/1: bitops: only emit .arch_extension mp if CONFIG_SMP

2013-11-20T23:05:53+00:00

Uwe reported a build failure when targetting a NOMMU platform with my
recent prefetch changes:

  arch/arm/lib/changebit.S: Assembler messages:
  arch/arm/lib/changebit.S:15: Error: architectural extension `mp' is
			not allowed for the current base architecture

This is due to use of the .arch_extension mp directive immediately prior
to an ALT_SMP(...) instruction. Whilst the ALT_SMP macro will expand to
nothing if !CONFIG_SMP, gas will still choke on the directive.

This patch fixes the issue by only emitting the sequence (including the
directive) if CONFIG_SMP=y.

Tested-by: Uwe Kleine-König 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: bitops: prefetch the destination word for write prior to strex

2013-09-30T15:42:56+00:00

The cost of changing a cacheline from shared to exclusive state can be
significant, especially when this is triggered by an exclusive store,
since it may result in having to retry the transaction.

This patch prefixes our atomic bitops implementation with prefetchw,
to try and grab the line in exclusive state from the start. The testop
macro is left alone, since the barrier semantics limit the usefulness
of prefetching data.

Acked-by: Nicolas Pitre 
Signed-off-by: Will Deacon

ARM: 7171/1: unwind: add unwind directives to bitops assembly macros

2011-11-26T21:58:53+00:00

The bitops functions (e.g. _test_and_set_bit) on ARM do not have unwind
annotations and therefore the kernel cannot backtrace out of them on a
fatal error (for example, NULL pointer dereference).

This patch annotates the bitops assembly macros with UNWIND annotations
so that we can produce a meaningful backtrace on error. Callers of the
macros are modified to pass their function name as a macro parameter,
enforcing that the macros are used as standalone function implementations.

Acked-by: Dave Martin 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 6653/1: bitops: Use BX instead of MOV PC,LR

2011-02-19T16:07:21+00:00

The kernel doesn't officially need to interwork, but using BX
wherever appropriate will help educate people into good assembler
coding habits.

BX is appropriate here because this code is predicated on
__LINUX_ARM_ARCH__ >= 6

Signed-off-by: Dave Martin 
Acked-by: Nicolas Pitre 
Signed-off-by: Russell King

ARM: bitops: switch set/clear/change bitops to use ldrex/strex

2011-02-02T21:23:25+00:00

Switch the set/clear/change bitops to use the word-based exclusive
operations, which are only present in a wider range of ARM architectures
than the byte-based exclusive operations.

Tested record:
- Nicolas Pitre: ext3,rw,le
- Sourav Poddar: nfs,le
- Will Deacon: ext3,rw,le
- Tony Lindgren: ext3+nfs,le

Reviewed-by: Nicolas Pitre 
Tested-by: Sourav Poddar 
Tested-by: Will Deacon 
Tested-by: Tony Lindgren 
Signed-off-by: Russell King

ARM: bitops: ensure set/clear/change bitops take a word-aligned pointer

2011-02-02T21:21:53+00:00

Add additional instructions to our assembly bitops functions to ensure
that they only operate on word-aligned pointers.  This will be necessary
when we switch these operations to use the word-based exclusive
operations.

Signed-off-by: Russell King