Selecting COMMON_CLK_AMLOGIC is not required as it is already selected by the SoC clock controller driver Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The 32-bit Meson SoCs use multiple Cortex-A9 (Meson8 and Meson8m2) or Cortex-A5 (Meson8b) CPU cores. These come with the "ARM global timer" and "Timer-Watchdog" (aka TWD, which provides both a per-cpu local timer and watchdog). Selecting ARM_GLOBAL_TIMER and HAVE_ARM_TWD allows us to add the timers to the SoC.dtsi files. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Currently there are no differences between the MACH_MESON8 and MACH_MESON8B Kconfig symbols (except the help text). Since both platforms are very similar (Meson8b being a slightly updated, cost-reduced version of Meson8 which even shares some peripherals with Meson8m2) no notable differences are expected in the future either. Suggested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the newly introduced compatible string for the Meson8m2 SoC. The existing Meson8 Kconfig entry is updated to also provide support for the Meson8m2 SoCs. The Meson8m2 SoC is mostly identical to the Meson8 SoC with just a few peripherals being updated. Both SoCs currently share the same pinctrl, clock and GPIO IRQ bindings. Thus the existing Kconfig entry is re-used to avoid duplication (the only cost is building a few extra DTBs). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Pull "Amlogic 32-bit DT changes for v4.16" from Kevin Hilman: - meson8: GPIO IRQ support - switch to stable UART bindings w/correct clock - add more L2 cache settings - drop unused ADC clock * tag 'amlogic-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: meson: enable MESON_IRQ_GPIO also for MACH_MESON8 ARM: dts: meson8: enable the GPIO interrupt controller ARM: dts: meson8b: use stable UART bindings with correct gate clock ARM: dts: meson8: use stable UART bindings with correct gate clock ARM: dts: meson: drop "sana" clock from SAR ADC ARM: dts: meson8: add more L2 cache settings ARM: dts: meson8b: add more L2 cache settings
Now that the GPIO interrupt controller also supports the Meson8 SoCs we can enable it via Kconfig. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Trivial fix to spelling mistake in pr_err error message Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
select MESON_IRQ_GPIO in Kconfig for Amlogic's meson8b SoC Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This adds the necessary SMP-operations and startup code to use the additional cores on the Amlogic Meson8/Meson8m2 (both are using the same sequence) and Meson8b (using a slightly difference sequence) SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> [add Meson8/Meson8m2 support and allow taking CPU cores offline as well] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock controller driver can also be used on Meson8 SoCs now that we have a separate compatible for it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>