linux-toradex.git/arch/arm/mach-msm/timer.c, branch v3.4-rc2

Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm

2012-03-29T23:53:48+00:00

Pull more ARM updates from Russell King.

This got a fair number of conflicts with the  split, but
also with some other sparse-irq and header file include cleanups.  They
all looked pretty trivial, though.

* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits)
  ARM: fix Kconfig warning for HAVE_BPF_JIT
  ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds
  ARM: 7349/1: integrator: convert to sparse irqs
  ARM: 7259/3: net: JIT compiler for packet filters
  ARM: 7334/1: add jump label support
  ARM: 7333/2: jump label: detect %c support for ARM
  ARM: 7338/1: add support for early console output via semihosting
  ARM: use set_current_blocked() and block_sigmask()
  ARM: exec: remove redundant set_fs(USER_DS)
  ARM: 7332/1: extract out code patch function from kprobes
  ARM: 7331/1: extract out insn generation code from ftrace
  ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format
  ARM: 7351/1: ftrace: remove useless memory checks
  ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path
  ARM: Versatile Express: add NO_IOPORT
  ARM: get rid of asm/irq.h in asm/prom.h
  ARM: 7319/1: Print debug info for SIGBUS in user faults
  ARM: 7318/1: gic: refactor irq_start assignment
  ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop
  ARM: 7315/1: perf: add support for the Cortex-A7 PMU
  ...

ARM: local timers: convert MSM to runtime registration interface

2012-03-13T13:45:55+00:00

Convert the MSM timers to the runtime registration interface.

Acked-by: Stephen Boyd 
Tested-by: David Brown 
Acked-by: David Brown 
Signed-off-by: Marc Zyngier

msm: timer: Support sched_clock()

2012-02-24T17:42:21+00:00

Now that sched_clock is mandatory on ARM it's simple to add
sched_clock support to the MSM timer code. Add it so that we get
more accurate sched_clock output than the jiffies based version
that's provided by default.

Signed-off-by: Stephen Boyd 
Acked-by: David Brown 
Signed-off-by: Marc Zyngier

msm: timer: Use clockevents_config_and_register()

2011-11-10T18:36:34+00:00

Don't open code the min/max delta logic. Use the generic
version instead. Also expand the number of bits we can handle
because there isn't anything that says we can't handle all 32
bits.

Before:
 max_delta_ns:   122880426391799
 min_delta_ns:   122070
 mult:           140737
 shift:          32

After:
 max_delta_ns:   131071523464981
 min_delta_ns:   122069
 mult:           70369
 shift:          31

Signed-off-by: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Signed-off-by: David Brown

msm: timer: Setup interrupt after registering clockevent

2011-11-10T18:36:33+00:00

Some bootloaders may leave a pending interrupt for the timer and
thus msm_timer_interrupt() has a check for a NULL event handler.
Unmask and register for the interrupt after registering the
clockevent so that we can get the NULL pointer check out of the
fast path.

Signed-off-by: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Signed-off-by: David Brown

msm: timer: Remove SoC specific #ifdefs

2011-11-10T18:36:33+00:00

The timer frequency is currently ifdefed in addition to setting
the DGT clock's divider value on SCORPIONMP targets. Setup the
frequency dynamically using the existing cpu_is_*() branches and
assign a custom clocksource read function for 7x01a to get the
shift out of the generic path.

Signed-off-by: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Signed-off-by: David Brown

msm: timer: Remove msm_clocks[] and simplify code

2011-11-10T18:36:33+00:00

We can simplify the timer code now that we only use the DGT for
the clocksource and the GPT for the clockevent. Get rid of the
msm_clocks[] array and propagate the changes throughout the code.
This reduces the lines of code in this file and improves
readability.

Signed-off-by: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Signed-off-by: David Brown

msm: timer: Fix ONESHOT mode interrupts

2011-11-10T18:36:33+00:00

MSM timers don't support an interrupt enable/disable bit.
Therefore, when the timer is free running it's possible for the
count to wrap and the match value to match again even though a
set_next_event() call hasn't been made since the last match.

Workaround the lack of an interrupt enable bit by explicitly
stopping the timer in the interrupt handler when the clockevent
is in ONESHOT mode. This should prevent any possibility of the
timer wrapping and matching more than once per set_next_event().

Signed-off-by: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Signed-off-by: David Brown

msm: timer: Use GPT for clockevents and DGT for clocksource

2011-11-10T18:36:33+00:00

The clocksource shouldn't stop ticking when the clockevent stops.
This is exactly what happens today with MSM timers. The same
hardware is used for both the clockevent and the clocksource
because the ratings of the two are the same.

Fix this by registering a clockevent based on the GPT and a
clocksource based on the DGT. This removes any other possible
configuration (e.g. a GPT clocksource and a DGT clockevent) but
that shouldn't be a big issue since we want higher precision
timing than high precision scheduling interrupts.

Signed-off-by: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Signed-off-by: David Brown

msm: timer: Cleanup #includes and #defines

2011-11-10T18:36:33+00:00

Remove unused/unnecessary #defines, #includes, and use the BIT
macro appropriately.

Signed-off-by: Stephen Boyd 
Signed-off-by: David Brown