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<title>linux-toradex.git/arch/arm/mm/Makefile, branch v3.2.5</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>ARM: v6k: introduce CPU_V6K option</title>
<updated>2011-02-02T21:23:26+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-01-17T15:08:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e399b1a4e1d205bdc816cb550d2064f2eb1ddc4c'/>
<id>e399b1a4e1d205bdc816cb550d2064f2eb1ddc4c</id>
<content type='text'>
Introduce a CPU_V6K configuration option for platforms to select if they
have a V6K CPU core.  This allows us to identify whether we need to
support ARMv6 CPUs without the V6K SMP extensions at build time.

Currently CPU_V6K is just an alias for CPU_V6, and all places which
reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K).

Select CPU_V6K from platforms which are known to be V6K-only.

Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Tested-by: Sourav Poddar &lt;sourav.poddar@ti.com&gt;
Tested-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Introduce a CPU_V6K configuration option for platforms to select if they
have a V6K CPU core.  This allows us to identify whether we need to
support ARMv6 CPUs without the V6K SMP extensions at build time.

Currently CPU_V6K is just an alias for CPU_V6, and all places which
reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K).

Select CPU_V6K from platforms which are known to be V6K-only.

Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Tested-by: Sourav Poddar &lt;sourav.poddar@ti.com&gt;
Tested-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: pgtable: collect up identity mapping functions</title>
<updated>2010-12-22T11:05:33+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-11-21T11:41:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=614dd0585f376a25c638abbed9c5fbd21d7baece'/>
<id>614dd0585f376a25c638abbed9c5fbd21d7baece</id>
<content type='text'>
We have two places where we create identity mappings - one when we bring
secondary CPUs online, and one where we setup some mappings for soft-
reboot.  Combine these two into a single implementation.  Also collect
the identity mapping deletion function.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
We have two places where we create identity mappings - one when we bring
secondary CPUs online, and one where we setup some mappings for soft-
reboot.  Combine these two into a single implementation.  Also collect
the identity mapping deletion function.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Remove DISCONTIGMEM support</title>
<updated>2010-07-16T09:57:35+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-05-07T16:40:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=be370302742ff9948f2a42b15cb2ba174d97b930'/>
<id>be370302742ff9948f2a42b15cb2ba174d97b930</id>
<content type='text'>
Everything should now be using sparsemem rather than discontigmem, so
remove the code supporting discontigmem from ARM.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Everything should now be using sparsemem rather than discontigmem, so
remove the code supporting discontigmem from ARM.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Ensure ARMv6/7 mm files are built using appropriate assembler options</title>
<updated>2010-01-12T19:02:05+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-01-12T19:02:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=aff7b4f86737f1ae364bf5ece9a9b8586ddb2db4'/>
<id>aff7b4f86737f1ae364bf5ece9a9b8586ddb2db4</id>
<content type='text'>
A kernel with both ARMv6 and ARMv7 selected results in build errors.
Fix this by specifying the proper architectures for these assembly
files.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
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<pre>
A kernel with both ARMv6 and ARMv7 selected results in build errors.
Fix this by specifying the proper architectures for these assembly
files.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'devel-stable' into devel</title>
<updated>2009-12-05T10:35:33+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2009-12-05T10:35:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0719dc341389882cc834ed18fc9b7fc6006b2b85'/>
<id>0719dc341389882cc834ed18fc9b7fc6006b2b85</id>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Add Tauros2 L2 cache controller support</title>
<updated>2009-11-27T20:43:21+00:00</updated>
<author>
<name>Lennert Buytenhek</name>
<email>buytenh@marvell.com</email>
</author>
<published>2009-11-24T17:33:52+00:00</published>
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<id>573a652fb0da50a1ff3fca2c67afd81138fd06d2</id>
<content type='text'>
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek &lt;buytenh@marvell.com&gt;
Signed-off-by: Saeed Bishara &lt;saeed@marvell.com&gt;
Signed-off-by: Nicolas Pitre &lt;nico@marvell.com&gt;
</content>
<content type='xhtml'>
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<pre>
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek &lt;buytenh@marvell.com&gt;
Signed-off-by: Saeed Bishara &lt;saeed@marvell.com&gt;
Signed-off-by: Nicolas Pitre &lt;nico@marvell.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: dma-mapping: split out vmregion code from dma coherent mapping code</title>
<updated>2009-11-24T17:41:34+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2009-11-19T15:07:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=13ccf3ad99a45052664f2c1a6c64899f9d778152'/>
<id>13ccf3ad99a45052664f2c1a6c64899f9d778152</id>
<content type='text'>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Acked-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</content>
<content type='xhtml'>
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<pre>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Acked-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()</title>
<updated>2009-10-02T21:34:32+00:00</updated>
<author>
<name>Kirill A. Shutemov</name>
<email>kirill@shutemov.name</email>
</author>
<published>2009-09-25T12:39:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4fb2847437d871fe579f820ceb18031db3359901'/>
<id>4fb2847437d871fe579f820ceb18031db3359901</id>
<content type='text'>
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.

Now we have three prefetch abort model:

  * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
  * ARMv6 - provides IFSR, but not IFAR;
  * ARMv7 - provides both IFSR and IFAR.

Signed-off-by: Kirill A. Shutemov &lt;kirill@shutemov.name&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.

Now we have three prefetch abort model:

  * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
  * ARMv6 - provides IFSR, but not IFAR;
  * ARMv7 - provides both IFSR and IFAR.

Signed-off-by: Kirill A. Shutemov &lt;kirill@shutemov.name&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into devel</title>
<updated>2009-03-26T23:10:11+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2009-03-26T23:10:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=542f869f1826f092606efd0c4c771f070d1314f5'/>
<id>542f869f1826f092606efd0c4c771f070d1314f5</id>
<content type='text'>
Conflicts:
	arch/arm/mm/Kconfig

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
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<pre>
Conflicts:
	arch/arm/mm/Kconfig

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Add support for FA526 v2</title>
<updated>2009-03-25T11:10:01+00:00</updated>
<author>
<name>Paulius Zaleckas</name>
<email>paulius.zaleckas@teltonika.lt</email>
</author>
<published>2009-03-25T11:10:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=28853ac8fe5221de74a14f1182d7b2b383dfd85c'/>
<id>28853ac8fe5221de74a14f1182d7b2b383dfd85c</id>
<content type='text'>
Adds support for Faraday FA526 core. This core is used at least by:
Cortina Systems Gemini and Centroid family
Cavium Networks ECONA family
Grain Media GM8120
Pixelplus ImageARM
Prolific PL-1029
Faraday IP evaluation boards

v2:
- move TLB_BTB to separate patch
- update copyrights

Signed-off-by: Paulius Zaleckas &lt;paulius.zaleckas@teltonika.lt&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Adds support for Faraday FA526 core. This core is used at least by:
Cortina Systems Gemini and Centroid family
Cavium Networks ECONA family
Grain Media GM8120
Pixelplus ImageARM
Prolific PL-1029
Faraday IP evaluation boards

v2:
- move TLB_BTB to separate patch
- update copyrights

Signed-off-by: Paulius Zaleckas &lt;paulius.zaleckas@teltonika.lt&gt;
</pre>
</div>
</content>
</entry>
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