linux-toradex.git/arch/arm/mm/proc-arm925.S, branch v3.2.63

ARM: mm: proc-arm925: Use the new processor struct macros

2011-07-07T14:31:09+00:00

Signed-off-by: Dave Martin

Fix common misspellings

2011-03-31T14:26:23+00:00

Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi

ARM: pm: add generic CPU suspend/resume support

2011-02-22T17:11:23+00:00

This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support.  This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.

Tested-by: Colin Cross 
Tested-by: Kukjin Kim 
Signed-off-by: Russell King

ARM: 6466/1: implement flush_icache_all for the rest of the CPUs

2010-10-28T12:54:28+00:00

Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for
CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
flush_icache_all(). It also implemented this for v6 and v7 but not
for v5 and backwards. Without the function pointer in place, we
will be calling wrong cache functions.

For example with ep93xx we get following:

    Unable to handle kernel paging request at virtual address ee070f38
    pgd = c0004000
    [ee070f38] *pgd=00000000
    Internal error: Oops: 80000005 [#1] PREEMPT
    last sysfs file:
    Modules linked in:
    CPU: 0    Not tainted  (2.6.36+ #1)
    PC is at 0xee070f38
    LR is at __dma_alloc+0x11c/0x2d0
    pc : []    lr : []    psr: 60000013
    sp : c581bde0  ip : 00000000  fp : c0472000
    r10: c0472000  r9 : 000000d0  r8 : 00020000
    r7 : 0001ffff  r6 : 00000000  r5 : c0472400  r4 : c5980000
    r3 : c03ab7e0  r2 : 00000000  r1 : c59a0000  r0 : c5980000
    Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
    Control: c000717f  Table: c0004000  DAC: 00000017
    Process swapper (pid: 1, stack limit = 0xc581a270)
    [] (__dma_alloc+0x11c/0x2d0)
    [] (dma_alloc_writecombine+0x1c/0x24)
    [] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
    [] (ep93xx_pcm_new+0x5c/0x88)
    [] (snd_soc_instantiate_cards+0x8a8/0xbc0)
    [] (soc_probe+0xfc/0x134)
    [] (platform_drv_probe+0x18/0x1c)
    [] (driver_probe_device+0xb0/0x16c)
    [] (bus_for_each_drv+0x48/0x84)
    [] (device_attach+0x50/0x68)
    [] (bus_probe_device+0x24/0x44)
    [] (device_add+0x2fc/0x44c)
    [] (platform_device_add+0x104/0x15c)
    [] (simone_init+0x60/0x94)
    [] (do_one_initcall+0xd0/0x1a4)

__dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
calling dmac_flush_range(). Now since the entries in the
arm920_cache_fns are shifted by one, we jump into address 0xee070f38
which is actually next instruction after the arm920_cache_fns
structure.

So implement flush_icache_all() for the rest of the supported CPUs
using a generic 'invalidate I cache' instruction.

Signed-off-by: Mika Westerberg 
Signed-off-by: Russell King

ARM: hotplug cpu: Keep processor information, startup code & __lookup_processor_type

2010-10-08T09:07:32+00:00

When hotplug CPU is enabled, we need to keep the list of supported CPUs,
their setup functions, and __lookup_processor_type in place so that we
can find and initialize secondary CPUs.  Move these into the __CPUINIT
section.

Signed-off-by: Russell King

ARM: Factor out common code from cpu_proc_fin()

2010-07-27T09:48:42+00:00

All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches.  Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)

This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.

Signed-off-by: Russell King

ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range

2010-02-15T15:22:23+00:00

These are now unused, and so can be removed.

Signed-off-by: Russell King 
Tested-By: Santosh Shilimkar

ARM: dma-mapping: provide per-cpu type map/unmap functions

2010-02-15T15:22:20+00:00

Signed-off-by: Russell King 
Tested-By: Santosh Shilimkar

ARM: add size argument to __cpuc_flush_dcache_page

2009-12-14T14:53:22+00:00

... and rename the function since it no longer operates on just
pages.

Signed-off-by: Russell King

ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()

2009-10-02T21:34:32+00:00

Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.

Now we have three prefetch abort model:

  * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
  * ARMv6 - provides IFSR, but not IFAR;
  * ARMv7 - provides both IFSR and IFAR.

Signed-off-by: Kirill A. Shutemov 
Signed-off-by: Russell King