linux-toradex.git/arch/arm/mm/proc-xscale.S, branch v3.3.4

ARM: proc-*.S: place cpu_reset functions into .idmap.text section

2011-12-06T14:04:14+00:00

The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.

This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.

Acked-by: Dave Martin 
Signed-off-by: Will Deacon

ARM: pm: only use preallocated page table during resume

2011-09-20T22:33:38+00:00

Only use the preallocated page table during the resume, not while
suspending.  This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.

Tested-by: Santosh Shilimkar 
Tested-by: Shawn Guo 
Tested-by: Lorenzo Pieralisi 
Signed-off-by: Russell King

ARM: pm: preallocate a page table for suspend/resume

2011-09-20T22:33:36+00:00

Preallocate a page table and setup an identity mapping for the MMU
enable code.  This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.

Tested-by: Santosh Shilimkar 
Tested-by: Shawn Guo 
Tested-by: Lorenzo Pieralisi 
Signed-off-by: Russell King

ARM: Fix build errors caused by adding generic macros

2011-07-21T16:49:54+00:00

Commit 66a625a (ARM: mm: proc-macros: Add generic proc/cache/tlb struct
definition macros) introduced build errors when PM_SLEEP is not enabled.
The per-CPU do_suspend/do_resume functions are defined via the
preprocessor to constant 0.  However, the macros which use these were
converted to assembly, resulting in undefined references to these
functions.  Fix that by moving the ! ifdef section into proc-macros.S
and deleting it from all effected proc-*.S files.

Acked-by: Dave Martin 
Signed-off-by: Russell King

ARM: mm: proc-xscale: Use new generic struct definition macros

2011-07-07T14:31:11+00:00

Without this patch, xscale_80200_A0_A1 is missing the
icache_flush_all entry, which would result in the wrong functions
being called at run-time.

This patch re-uses xscale_icache_flush_all for
xscale_80200_A0_A1_cache_fns.

Signed-off-by: Dave Martin

ARM: Fix .size directive for xscale_dma_a0_map_area

2011-04-28T09:56:31+00:00

gas used to accept (and ignore?) .size directives which referred to
undefined symbols, as this does.  In binutils 2.21 these are treated
as fatal errors.

Signed-off-by: Ben Hutchings 
Signed-off-by: Eric Miao

ARM: Make consolidated PM sleep code depend on PM_SLEEP

2011-04-02T09:08:55+00:00

CONFIG_PM is now set whenever we support either runtime PM in addition
to suspend and hibernate.  This causes build errors when runtime PM is
enabled on a platform, but the CPU does not have the appropriate support
for suspend.

So, switch this code to use CONFIG_PM_SLEEP rather than CONFIG_PM to
allow runtime PM to be enabled without causing build errors.

Signed-off-by: Russell King

ARM: pm: add generic CPU suspend/resume support

2011-02-22T17:11:23+00:00

This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support.  This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.

Tested-by: Colin Cross 
Tested-by: Kukjin Kim 
Signed-off-by: Russell King

ARM: pgtable: provide RDONLY page table bit rather than WRITE bit

2010-12-22T11:05:35+00:00

Signed-off-by: Russell King

ARM: 6466/1: implement flush_icache_all for the rest of the CPUs

2010-10-28T12:54:28+00:00

Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for
CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
flush_icache_all(). It also implemented this for v6 and v7 but not
for v5 and backwards. Without the function pointer in place, we
will be calling wrong cache functions.

For example with ep93xx we get following:

    Unable to handle kernel paging request at virtual address ee070f38
    pgd = c0004000
    [ee070f38] *pgd=00000000
    Internal error: Oops: 80000005 [#1] PREEMPT
    last sysfs file:
    Modules linked in:
    CPU: 0    Not tainted  (2.6.36+ #1)
    PC is at 0xee070f38
    LR is at __dma_alloc+0x11c/0x2d0
    pc : []    lr : []    psr: 60000013
    sp : c581bde0  ip : 00000000  fp : c0472000
    r10: c0472000  r9 : 000000d0  r8 : 00020000
    r7 : 0001ffff  r6 : 00000000  r5 : c0472400  r4 : c5980000
    r3 : c03ab7e0  r2 : 00000000  r1 : c59a0000  r0 : c5980000
    Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
    Control: c000717f  Table: c0004000  DAC: 00000017
    Process swapper (pid: 1, stack limit = 0xc581a270)
    [] (__dma_alloc+0x11c/0x2d0)
    [] (dma_alloc_writecombine+0x1c/0x24)
    [] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
    [] (ep93xx_pcm_new+0x5c/0x88)
    [] (snd_soc_instantiate_cards+0x8a8/0xbc0)
    [] (soc_probe+0xfc/0x134)
    [] (platform_drv_probe+0x18/0x1c)
    [] (driver_probe_device+0xb0/0x16c)
    [] (bus_for_each_drv+0x48/0x84)
    [] (device_attach+0x50/0x68)
    [] (bus_probe_device+0x24/0x44)
    [] (device_add+0x2fc/0x44c)
    [] (platform_device_add+0x104/0x15c)
    [] (simone_init+0x60/0x94)
    [] (do_one_initcall+0xd0/0x1a4)

__dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
calling dmac_flush_range(). Now since the entries in the
arm920_cache_fns are shifted by one, we jump into address 0xee070f38
which is actually next instruction after the arm920_cache_fns
structure.

So implement flush_icache_all() for the rest of the supported CPUs
using a generic 'invalidate I cache' instruction.

Signed-off-by: Mika Westerberg 
Signed-off-by: Russell King