linux-toradex.git/arch/arm/vfp/vfpdouble.c, branch v3.2.40 Linux kernel for Apalis and Colibri modules [ARM] vfp: fix fuitod/fsitod instructions 2008-01-10T17:07:08+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2008-01-10T17:07:08+00:00 90e6b048365950416419c031f2f2d9a8afb5b70c These two instructions exceptionally take a single precision register as their operand. This means we can't use vfp_get_dm() to read the register number - we need to use vfp_get_sm() instead. Add a flag to indicate this exception to the general rule. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
These two instructions exceptionally take a single precision register
as their operand.  This means we can't use vfp_get_dm() to read the
register number - we need to use vfp_get_sm() instead.  Add a flag to
indicate this exception to the general rule.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 4630/1: Fix the vector stride of the double vector instruction. 2007-10-20T22:42:22+00:00 Takashi Ohmasa ohmasa.takashi@jp.panasonic.com 2007-10-19T12:59:15+00:00 b9a5ce3cae2f6d04c521204004a36be46656ec7b The vector stride of the double-precision vector instructions must be changed to 1-2 from even 2-4, because the double registers numbering has been changed to 0-15 from even 0-30 by 1356c1948da967bc1d4c663762bfe21dfcec4b2f commit. Signed-off-by: Takashi Ohmasa <ohmasa.takashi@jp.panasonic.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The vector stride of the double-precision vector instructions must be changed
to 1-2 from even 2-4, because the double registers numbering has been
changed to 0-15 from even 0-30 by
1356c1948da967bc1d4c663762bfe21dfcec4b2f commit.

Signed-off-by: Takashi Ohmasa <ohmasa.takashi@jp.panasonic.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] Remove unnecessary asm/ptrace.h from VFP support code 2007-04-22T09:56:40+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2007-04-22T09:56:40+00:00 7531a1c2c4477f63688871c1648d828f55313d42 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3899/1: Fix the normalization of the denormal double precision number. 2006-10-28T09:15:31+00:00 Takashi Ohmasa ohmasa.takashi@com.rmk.(none) 2006-10-23T07:30:35+00:00 e816d71a50a714b532e3965364f3f53c23a53d42 The significand should be shifted until the value of bit [62] is 1 to normalize the denormal double number. Signed-off-by: Takashi Ohmasa <ohmasa.takashi@jp.panasonic.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The significand should be shifted until the value of bit [62] is 1
to normalize the denormal double number.

Signed-off-by: Takashi Ohmasa <ohmasa.takashi@jp.panasonic.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] Cleanups for 4cc9bd2eaa1063c68341c1c00e66660adcfdf254 2006-09-25T09:34:59+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2006-09-21T16:00:08+00:00 baf97ce6eda5891ee45fae9c1b06db855bb697e1 - Document the meaning for OP_SCALAR, OP_SD and add OP_DD. - Formatting cleanups - Remove now redundant code for making compare instructions operate on scalar values. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
- Document the meaning for OP_SCALAR, OP_SD and add OP_DD.
- Formatting cleanups
- Remove now redundant code for making compare instructions
  operate on scalar values.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3789/4: Fix VFP emulation to ignore VECITR for scalar instruction 2006-09-25T09:34:06+00:00 Gen FUKATSU fukatsu.gen@jp.panasonic.com 2006-09-21T13:08:24+00:00 4cc9bd2eaa1063c68341c1c00e66660adcfdf254 VECITR in Floating-Point Exception register indicates the number of remaining short vector iterations after a potential exception was detected. In case of exception caused by scalar instructions, VECITR is NOT updated. Therefore emulation for VFP must ignore VECITR field and treat "veclen" as zero when recognizing scalar instructing. Signed-off-by: Gen Fukatsu <fukatsu.gen@jp.panasonic.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
VECITR in Floating-Point Exception register indicates the number of
remaining short vector iterations after a potential exception was
detected.

In case of exception caused by scalar instructions, VECITR is NOT updated.
Therefore emulation for VFP must ignore VECITR field
and treat "veclen" as zero when recognizing scalar instructing.

Signed-off-by: Gen Fukatsu <fukatsu.gen@jp.panasonic.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3750/3: Fix double VFP emulation for EABI kernels 2006-08-30T14:06:39+00:00 Daniel Jacobowitz drow@false.org 2006-08-30T14:06:39+00:00 0355b3e039c621d15321fd0d5cf72d8bdb8f723d Patch from Daniel Jacobowitz vfp_put_double didn't work in a CONFIG_AEABI kernel. By swapping the arguments, we arrange for them to be in the same place regardless of ABI. I made the same change to vfp_put_float for consistency. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Patch from Daniel Jacobowitz

vfp_put_double didn't work in a CONFIG_AEABI kernel.  By swapping
the arguments, we arrange for them to be in the same place regardless
of ABI.  I made the same change to vfp_put_float for consistency.

Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3758/1: Preserve signalling NaNs in conversion 2006-08-27T11:42:14+00:00 Daniel Jacobowitz drow@false.org 2006-08-27T11:42:14+00:00 b53a2b41f156a9c9b62c14502037cbc15bc08b54 Patch from Daniel Jacobowitz The fcvtds and fcvtsd instructions were generating a qnan bit pattern for both quiet and signalling NaNs. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Patch from Daniel Jacobowitz

The fcvtds and fcvtsd instructions were generating a qnan bit pattern
for both quiet and signalling NaNs.

Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3749/3: Correct VFP single/double conversion emulation 2006-08-27T11:42:10+00:00 Daniel Jacobowitz drow@false.org 2006-08-27T11:42:10+00:00 c29ecac18cb740ae845db14963ac586c53962453 Patch from Daniel Jacobowitz The fcvtsd/fcvtds emulation was left behind when the numbering of double precision registers was changed from 0-30 to 0-15. Both conversion instructions were writing their results to the wrong register. Also, the conversion instructions should stop after the first element even if a vector length is specified. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Patch from Daniel Jacobowitz

The fcvtsd/fcvtds emulation was left behind when the numbering of double
precision registers was changed from 0-30 to 0-15.  Both conversion
instructions were writing their results to the wrong register.  Also,
the conversion instructions should stop after the first element even
if a vector length is specified.

Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] vfp: fix leak of VFP_NAN_FLAG into FPSCR 2006-04-25T19:41:27+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2006-04-25T19:41:27+00:00 928bd1b4709045355fad8bf858904884c0a1e87f The VFP code can leak VFP_NAN_FLAG into the FPSCR. It doesn't correspond to any real FPSCR bit (and overlaps one of the exception flags). Bug report from Daniel Jacobowitz Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The VFP code can leak VFP_NAN_FLAG into the FPSCR. It doesn't correspond
to any real FPSCR bit (and overlaps one of the exception flags).

Bug report from Daniel Jacobowitz

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>