linux-toradex.git/arch/arm64/boot/dts/Makefile, branch master Linux kernel for Apalis and Colibri modules arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board 2025-11-21T20:12:26+00:00 Albert Yang yangzh0906@thundersoft.com 2025-10-16T12:05:56+00:00 c03a37773bf0eaf3b4aa08143e2faf7400f152ad Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, and interrupt controller. Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
Add device tree support for the Black Sesame Technologies (BST) C1200
CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
family.
The changes include:
- Adding a new BST device tree directory
- Adding Makefile entries to build the BST platform device trees
- Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
This board features a quad-core Cortex-A78 CPU, and various peripherals
including UART, and interrupt controller.

Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc 2025-07-23T20:19:15+00:00 Arnd Bergmann arnd@arndb.de 2025-07-23T20:19:14+00:00 05a623030b3cc2250755e4d4d6b1440a03aed674 ARM Devicetrees for v6.17 Sophgo: Add support for Duo Module 01 Evaluation Board. This board uses SG2000(old codename CV181xH), which is dual-arch, RISC-V and ARM64. This patch add the support for ARM64. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: arm64: defconfig: Enable rudimentary Sophgo SG2000 support arm64: Add SOPHGO SOC family Kconfig support arm64: dts: sophgo: Add Duo Module 01 Evaluation Board arm64: dts: sophgo: Add Duo Module 01 arm64: dts: sophgo: Add initial SG2000 SoC device tree Link: https://lore.kernel.org/r/MAUPR01MB11072C4B088AAC02268044E95FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
ARM Devicetrees for v6.17

Sophgo:

Add support for Duo Module 01 Evaluation Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch add the support for ARM64.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux:
  arm64: defconfig: Enable rudimentary Sophgo SG2000 support
  arm64: Add SOPHGO SOC family Kconfig support
  arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
  arm64: dts: sophgo: Add Duo Module 01
  arm64: dts: sophgo: Add initial SG2000 SoC device tree

Link: https://lore.kernel.org/r/MAUPR01MB11072C4B088AAC02268044E95FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board 2025-07-23T01:56:27+00:00 Alexander Sverdlin alexander.sverdlin@gmail.com 2025-06-12T13:28:12+00:00 aa3f38f5dc4cc463e620833b71362a805ac169ea Duo Module 01 Evaluation Board contains Sophgo Duo Module 01 SMD SoM, Ethernet+USB switch, microSD slot, etc... Add only support for UART0 (console) and microSD slot. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250612132844.767216-5-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> 
Duo Module 01 Evaluation Board contains Sophgo Duo Module 01
SMD SoM, Ethernet+USB switch, microSD slot, etc...
Add only support for UART0 (console) and microSD slot.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250612132844.767216-5-alexander.sverdlin@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Merge branch 'newsoc/axiado' into soc/newsoc 2025-07-22T20:30:38+00:00 Arnd Bergmann arnd@arndb.de 2025-07-22T20:30:38+00:00 dceb36675b5375955cdbd44ad693c080359fecb8 Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>: The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53 cores, secure vault, hardware firewall, and AI acceleration engines. This initial support enables basic bring-up of the SoC and evaluation platform with CPU, timer, UART, and I3C functionality. The series begins by adding the "axiado" vendor prefix and compatible strings for the SoC and board. It then introduces the device tree files and minimal ARCH_AXIADO platform support in arm64. * newsoc/axiado: MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation 
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>:

The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53
cores, secure vault, hardware firewall, and AI acceleration engines. This
initial support enables basic bring-up of the SoC and evaluation platform
with CPU, timer, UART, and I3C functionality.

The series begins by adding the "axiado" vendor prefix and compatible
strings for the SoC and board. It then introduces the device tree files
and minimal ARCH_AXIADO platform support in arm64.

* newsoc/axiado:
  MAINTAINERS: Add entry for Axiado
  arm64: defconfig: enable the Axiado family
  arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
  arm64: add Axiado SoC family
  dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
  dt-bindings: serial: cdns: add Axiado AX3000 UART controller
  dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
  dt-bindings: gpio: cdns: convert to YAML
  dt-bindings: arm: axiado: add AX3000 EVK compatible strings
  dt-bindings: vendor-prefixes: Add Axiado Corporation
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board 2025-07-22T20:30:18+00:00 Harshit Shah hshah@axiado.com 2025-07-22T20:15:36+00:00 1f70557790011fbf6f6ba4dd85910e427e12d2f8 Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores, Secure Vault, AI Engine and Firewall. It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C controllers on the AX3000 evaluation board. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Harshit Shah <hshah@axiado.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.

It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: dts: cix: Add sky1 base dts initial support 2025-07-21T15:14:55+00:00 Peter Chen peter.chen@cixtech.com 2025-07-21T14:44:59+00:00 80be23bb20eab1a89cf585b3bdee0e257d23f5e0 CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, and Orion O6 is the motherboard launched by Radxa. See below for detail: https://docs.radxa.com/en/orion/o6/getting-started/introduction In this commit, it only adds limited components for running initramfs at Orion O6. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com> Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech,
and Orion O6 is the motherboard launched by Radxa. See below for
detail:
https://docs.radxa.com/en/orion/o6/getting-started/introduction

In this commit, it only adds limited components for running initramfs
at Orion O6.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: dts: Add initial support for Blaize BLZP1600 CB2 2024-12-13T15:57:24+00:00 Nikolaos Pasaloukos nikolaos.pasaloukos@blaize.com 2024-12-04T16:05:27+00:00 2e976f19d9c2863e0f97bf598f42e87efe5d9784 Add support for the Blaize CB2 development board based on the BLZP1600 SoC. This consists of a Carrier-Board-2 and a System-on-Module. Both BLZP1600 SoM and CB2 are available as products. CB2 (Pathfinder) has multiple peripherals like UART, I2C, SPI, GPIO, CSI (camera), DSI (display), USB-3.0 and Ethernet. Enable support for the Cryptocell, UART and I2C which are already fully supported by the drivers. The blaize-blzp1600.dtsi is the common part for the SoC, blaize-blzp1600-som.dtsi is the common part for the SoM and blaize-blzp1600-cb2.dts is the board specific file. Co-developed-by: James Cowgill <james.cowgill@blaize.com> Signed-off-by: James Cowgill <james.cowgill@blaize.com> Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com> Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com> Co-developed-by: Neil Jones <neil.jones@blaize.com> Signed-off-by: Neil Jones <neil.jones@blaize.com> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
Add support for the Blaize CB2 development board based on
the BLZP1600 SoC. This consists of a Carrier-Board-2 and a
System-on-Module.

Both BLZP1600 SoM and CB2 are available as products.
CB2 (Pathfinder) has multiple peripherals like UART, I2C,
SPI, GPIO, CSI (camera), DSI (display), USB-3.0 and Ethernet.

Enable support for the Cryptocell, UART and I2C which are
already fully supported by the drivers.

The blaize-blzp1600.dtsi is the common part for the SoC,
blaize-blzp1600-som.dtsi is the common part for the SoM and
blaize-blzp1600-cb2.dts is the board specific file.

Co-developed-by: James Cowgill <james.cowgill@blaize.com>
Signed-off-by: James Cowgill <james.cowgill@blaize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
Co-developed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board 2024-06-27T08:10:18+00:00 Daniel Danzberger dd@embedd.com 2024-03-09T09:32:15+00:00 ab52c59103002b49f2455371e4b9c56ba3ef1781 Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Daniel Danzberger <dd@embedd.com> Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/f05a36dd7e8ef34ead8a63aa10fcffb542229404.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
Board's dts file, as well as the required Makefiles.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Daniel Danzberger <dd@embedd.com>
Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/f05a36dd7e8ef34ead8a63aa10fcffb542229404.1709975956.git.lorenzo@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
arm64: dts: st: add stm32mp257f-ev1 board support 2023-06-08T14:01:45+00:00 Alexandre Torgue alexandre.torgue@foss.st.com 2021-11-18T11:26:49+00:00 1c89075497bb6347fcda99442f3505043b4d2fdf Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> 
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
arm64: dts: nuvoton: Add initial NPCM8XX device tree 2022-07-19T13:41:04+00:00 Tomer Maimon tmaimon77@gmail.com 2022-07-17T09:16:07+00:00 6cc82f07fc340570811c18d7241b54c91aa4ac19 This adds initial device tree support for the Nuvoton NPCM845 Board Management controller (BMC) SoC family. The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and have various peripheral IPs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
This adds initial device tree support for the Nuvoton NPCM845 Board
Management controller (BMC) SoC family.

The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and have
various peripheral IPs.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>