Pull SoC devicetree updates from Arnd Bergmann:
 "A number of SoC platforms are adding modernized variants of their
  already supported chips time, with a total of 12 new SoCs, and two
  older SoC getting removed:

   - Qualcomm Glymur is a compute SoC using 18 Oryon-2 CPU cores
   - Qualcomm Mahua is a variant of Glymur with only 12 CPU cores, but
     largely identical.
   - Qualcomm Eliza is an embeded platform for mobile phone (SM7750) and
     IOT (QC7790S/M) workloads
   - Qualcomm IPQ5210 is a wireless networking SoC using Cortex-A53
     cores
   - Qualcomm apq8084 and ipq806x had only rudimentary support but no
     actual products using them, so they are now gone.
   - Axis ARTPEC-9 is a follow-up to the ARTPEC-8 embedded SoC, using
     the Samsung SoC platform but now with Cortex-A55 cores
   - ARM Zena is a virtual platform in FVP using Cortex-A720AE cores,
     with additional versions planned to be merged in the future.
   - ARM corstone-1000-a320 is a reference platform for IOT, using
     low-end Cortex-A320 cores
   - Microchip LAN9691 is an updated 64-bit variant of the arm32 lan966x
     series of networking SoCs
   - Microchip PIC64GX is an embedded RISC-V chip using SIFIVE U54 CPU
     cores
   - Rockchip RV1103B is the low-end 32-bit single-core vision processor
   - Renesas RZ/G3L (r9a08g046) is an industrial embedded chip using
     Cortex-A55 cores, similar to the G3E and G3S variants we already
     supported.
   - NXP S32N79 is an automotive SoC using Cortex-A78AE cores, a
     significant upgrade from the older S32V and S32G series

  These all come with at least one reference board or an initial product
  using these, in total there are 67 newly added boards. The ones for
  already supported SoCs are:

   - Two more Aspeed BMC based boards
   - Three older tablets based on 32-bit OMAP4 and Exynos5 SoCs
   - One Set-top-box based on Allwinner H6
   - 22 additional industrial/embedded boards using 64-bit NXP i.MX8M or
     i.MX9 SoCs
   - 20 Qualcomm SoC based machines across all possible markets:
     workstation, gaming, laptop, phone, networking, reference, ...
   - Three more Rockchips rk35xx based boards
   - Four variants of the Toradex Verdin using TI AM62

  Other notable bits are:

   - A cleanup for the 32-bit Tegra paz00 board moved the last board
     specific code on Tegra into equivalent dts syntax.
   - There continues to be a significant number of fixes for static
     checking of dtc syntax, but it feels like this is slowing down,
     hopefully getting into a state where most known issues are
     addressed
   - Additional hardware support for many existing boards across SoC
     families, notably Qualcomm, Broadcom, i.MX2, i.MX6, Rockchips,
     STM32, Mediatek, Tegra, TI and Microchip"

* tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (841 commits)
  arm64: dts: ti: k3: Use memory-region-names for r5f
  ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards
  ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif
  ARM: dts: imx25: rename node name tcq to touchscreen
  ARM: dts: imx: b850v3: Disable unused usdhc4
  ARM: dts: imx: b850v3: Define GPIO line names
  ARM: dts: imx: b850v3: Use alphabetical sorting
  ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning
  ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps
  ARM: dts: imx7ulp: Add CPU clock and OPP table support
  ARM: dts: imx7-mba7: Deassert BOOT_EN after boot
  ARM: dts: tqma7: add boot phase properties
  ARM: dts: imx7s: add boot phase properties
  ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems
  ARM: dts: mba6ulx: add boot phase properties
  ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties
  ARM: dts: imx6ul/imx6ull: add boot phase properties
  ARM: dts: imx6qdl-mba6: add boot phase properties
  ARM: dts: imx6qdl-tqma6: add boot phase properties
  ARM: dts: imx6qdl: add boot phase properties
  ...

When attach to PC Type-A port, the USB device controller does not function
at all. Because it is configured as source-only and a Type-A port doesn't
support PD capability, a data role swap is impossible.

Actually, PTN5110THQ is configured for Source role only at POR, but after
POR it can operate as a DRP (Dual-Role Power). By switching the power-role
to dual, the port can operate as a sink and enter device mode when attach
to Type-A port.

Since the board design uses EN_SRC to control the 5V VBUS path and EN_SNK
to control the 12V VBUS output, to avoid outputting a higher VBUS when in
sink role, we set the operation current limit to 0mA so that SW will not
control EN_SNK at all.

Fixes: 2faf4ebcee2e5 ("arm64: dts: freescale: imx8qxp-mek: enable cadence usb3")
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

When attach to PC Type-A port, the USB device controller does not function
at all. Because it is configured as source-only and a Type-A port doesn't
support PD capability, a data role swap is impossible.

Actually, PTN5110THQ is configured for Source role only at POR, but after
POR it can operate as a DRP (Dual-Role Power). By switching the power-role
to dual, the port can operate as a sink and enter device mode when attach
to Type-A port.

Since the board design uses EN_SRC to control the 5V VBUS path and EN_SNK
to control the 12V VBUS output, to avoid outputting a higher VBUS when in
sink role, we set the operation current limit to 0mA so that SW will not
control EN_SNK at all.

Fixes: b237975b2cd58 ("arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes")
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

LX2162A Clearfog has four LEDs attached physically to the 4-port SFP
connector. They are intended to show information relating to network
interface status.

Select "netdev" as default trigger for each LED, and link each one to
the respective dpmac instance as trigger-source.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

Add aliases for crypto accelerator and rtc0 ensuring that on-SoM RTC and
the SoC A72 domain crypto accelerator are assigned first index.

Further set model and compatible strings which are informative but
overridden by actual boards.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

Add alias for rtc0 ensuring that on-COM RTC is assigned first index.

Note that fsl-lx2160a.dtsi already defines an alias for rtc1 which
implicitly achieved the same result.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
support bus recovery") introduced pinmux nodes for lx2160 i2c
interfaces, allowing runtime change between i2c and gpio functions
implementing bus recovery.

However, the dynamic configuration area (overwrite MUX) used by the
pinctrl-single driver initially reads as zero and does not reflect the
actual hardware state set by the Reset Configuration Word (RCW) at
power-on.

Because multiple groups of pins are configured from a single 32-bit
register, the first write from the pinctrl driver unintentionally clears
all other bits to zero.

Add description for all bits of RCWSR12 register, allowing boards to
explicitly define and restore their intended hardware state.

This includes i2c, gpio, flextimer, spi, can and sdhc functions.

Other configuration words, i.e. RCWSR13 & RCWSR14 may be added in the
future for boards setting non-zero values there.

Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

Replace some stray zeros from decimal to hexadecimal format within
pinmux nodes.

No functional change intended.

Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

LX2160A pinmux is done in groups by various length bitfields within
configuration registers.

In particular i2c sda/scl pins are always configured together. Therefore
bus recovery may control both sda and scl.

When pinmux nodes and bus recovery was enabled originally for LX2160,
only the scl-gpios were added to the i2c controller nodes.

Add references to sda-gpios for each i2c controller.

Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

LX2160A pinmux is done in groups by various length bitfields within
configuration registers.

Each group of pins is named in the reference manual after a primary
function using soc-specific naming, e.g. IIC1 (for i2c0).

Hardware block numbering starts from zero in device-tree but one in the
reference manual.

Rename the already defined pinmux nodes originally added for changing
i2c pins between i2c and gpio functions reflecting the reference manual
name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
label.

Specifically, drop the "_scl" suffix from the I2C labels because the
nodes actually configure both SDA and SCL pins together. Instead add
"_pins" suffix to avoid conflicts with I2C controller labels.

For GPIO functions, include the specific controller and pin numbers in
the label to clarify they are generic GPIOs and help spot mistakes.

No functional change intended.

Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>