linux-toradex.git/arch/arm64/include/asm/cacheflush.h, branch v4.12

treewide: decouple cacheflush.h and set_memory.h

2017-05-09T00:15:14+00:00

Now that all call sites, completely decouple cacheflush.h and
set_memory.h

[sfr@canb.auug.org.au: kprobes/x86: merge fix for set_memory.h decoupling]
  Link: http://lkml.kernel.org/r/20170418180903.10300fd3@canb.auug.org.au
Link: http://lkml.kernel.org/r/1488920133-27229-17-git-send-email-labbott@redhat.com
Signed-off-by: Laura Abbott 
Signed-off-by: Stephen Rothwell 
Acked-by: Catalin Marinas 
Acked-by: Mark Rutland 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

treewide: move set_memory_* functions away from cacheflush.h

2017-05-09T00:15:13+00:00

Patch series "set_memory_* functions header refactor", v3.

The set_memory_* APIs came out of a desire to have a better way to
change memory attributes.  Many of these attributes were linked to cache
functionality so the prototypes were put in cacheflush.h.  These days,
the APIs have grown and have a much wider use than just cache APIs.  To
support this growth, split off set_memory_* and friends into a separate
header file to avoid growing cacheflush.h for APIs that have nothing to
do with caches.

Link: http://lkml.kernel.org/r/1488920133-27229-2-git-send-email-labbott@redhat.com
Signed-off-by: Laura Abbott 
Acked-by: Russell King 
Acked-by: Mark Rutland 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

arm64: mm: add set_memory_valid()

2017-04-05T17:27:53+00:00

This function validates and invalidates PTE entries, and will be utilized
in kdump to protect loaded crash dump kernel image.

Signed-off-by: AKASHI Takahiro 
Reviewed-by: Ard Biesheuvel 
Signed-off-by: Catalin Marinas

arm64: Remove I-cache invalidation from flush_cache_range()

2016-11-23T18:05:52+00:00

The flush_cache_range() function (similarly for flush_cache_page()) is
called when the kernel is changing an existing VA->PA mapping range to
either a new PA or to different attributes. Since ARMv8 has PIPT-like
D-caches, this function does not need to perform any D-cache
maintenance. The I-cache maintenance is already handled via set_pte_at()
and flush_cache_range() cannot anyway guarantee that there are no cache
lines left after invalidation due to the speculative loads.

This patch makes flush_cache_range() a no-op.

Signed-off-by: Catalin Marinas

arm64: Add uprobe support

2016-11-07T18:15:21+00:00

This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found
working
    1. Step-able instructions, like sub, ldr, add etc.
    2. Simulation-able like ret, cbnz, cbz etc.
    3. uretprobe
    4. Reject-able instructions like sev, wfe etc.
    5. trapped and abort xol path
    6. probe at unaligned user address.
    7. longjump test cases

Currently it does not support aarch32 instruction probing.

Signed-off-by: Pratyush Anand 
Signed-off-by: Catalin Marinas

arm64: mm: convert __dma_* routines to use start, size

2016-08-22T09:00:48+00:00

__dma_* routines have been converted to use start and size instread of
start and end addresses. The patch was origianlly for adding
__clean_dcache_area_poc() which will be used in pmem driver to clean
dcache to the PoC(Point of Coherency) in arch_wb_cache_pmem().

The functionality of __clean_dcache_area_poc()  was equivalent to
__dma_clean_range(). The difference was __dma_clean_range() uses the end
address, but __clean_dcache_area_poc() uses the size to clean.

Thus, __clean_dcache_area_poc() has been revised with a fallthrough
function of __dma_clean_range() after the change that __dma_* routines
use start and size instead of using start and end.

As a consequence of using start and size, the name of __dma_* routines
has also been altered following the terminology below:
    area: takes a start and size
    range: takes a start and end

Reviewed-by: Robin Murphy 
Signed-off-by: Kwangwoo Lee 
Signed-off-by: Will Deacon

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

2016-03-25T02:13:59+00:00

Pull second set of arm64 updates from Catalin Marinas:

 - KASLR bug fixes: use callee-saved register, boot-time I-cache
   maintenance

 - inv_entry asm macro fix (EL0 check typo)

 - pr_notice("Virtual kernel memory layout...") splitting

 - Clean-ups: use p?d_set_huge consistently, allow preemption around
   copy_to_user_page, remove unused __local_flush_icache_all()

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: mm: allow preemption in copy_to_user_page
  arm64: consistently use p?d_set_huge
  arm64: kaslr: use callee saved register to preserve SCTLR across C call
  arm64: Split pr_notice("Virtual kernel memory layout...") into multiple pr_cont()
  arm64: drop unused __local_flush_icache_all()
  arm64: fix KASLR boot-time I-cache maintenance
  arm64/kernel: fix incorrect EL0 check in inv_entry macro

arm64: drop unused __local_flush_icache_all()

2016-03-21T12:10:03+00:00

After commit 65da0a8e34a8 ("arm64: use non-global mappings for UEFI
runtime regions"), nobody use __local_flush_icache_all() anymore,
so drop it.

Signed-off-by: Kefeng Wang 
Acked-by: Mark Rutland 
Signed-off-by: Catalin Marinas

asm-generic: Consolidate mark_rodata_ro()

2016-02-22T07:51:37+00:00

Instead of defining mark_rodata_ro() in each architecture, consolidate it.

Signed-off-by: Kees Cook 
Acked-by: Will Deacon 
Cc: Andrew Morton 
Cc: Andy Gross 
Cc: Andy Lutomirski 
Cc: Ard Biesheuvel 
Cc: Arnd Bergmann 
Cc: Ashok Kumar 
Cc: Borislav Petkov 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Catalin Marinas 
Cc: Dan Williams 
Cc: David Brown 
Cc: David Hildenbrand 
Cc: Denys Vlasenko 
Cc: Emese Revfy 
Cc: H. Peter Anvin 
Cc: Helge Deller 
Cc: James E.J. Bottomley 
Cc: Linus Torvalds 
Cc: Luis R. Rodriguez 
Cc: Marc Zyngier 
Cc: Mark Rutland 
Cc: Mathias Krause 
Cc: Michael Ellerman 
Cc: Nicolas Pitre 
Cc: PaX Team 
Cc: Paul Gortmaker 
Cc: Peter Zijlstra 
Cc: Ross Zwisler 
Cc: Russell King 
Cc: Rusty Russell 
Cc: Stephen Boyd 
Cc: Thomas Gleixner 
Cc: Toshi Kani 
Cc: kernel-hardening@lists.openwall.com
Cc: linux-arch 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-parisc@vger.kernel.org
Link: http://lkml.kernel.org/r/1455748879-21872-2-git-send-email-keescook@chromium.org
Signed-off-by: Ingo Molnar

arm64: Use PoU cache instr for I/D coherency

2015-12-17T11:07:13+00:00

In systems with three levels of cache(PoU at L1 and PoC at L3),
PoC cache flush instructions flushes L2 and L3 caches which could affect
performance.
For cache flushes for I and D coherency, PoU should suffice.
So changing all I and D coherency related cache flushes to PoU.

Introduced a new __clean_dcache_area_pou API for dcache flush till PoU
and provided a common macro for __flush_dcache_area and
__clean_dcache_area_pou.

Also, now in __sync_icache_dcache, icache invalidation for non-aliasing
VIPT icache is done only for that particular page instead of the earlier
__flush_icache_all.

Reviewed-by: Catalin Marinas 
Reviewed-by: Mark Rutland 
Signed-off-by: Ashok Kumar 
Signed-off-by: Will Deacon