linux-toradex.git/arch/arm64/include/uapi/asm/kvm.h, branch v3.17

arm64: KVM: Enable minimalistic support for Cortex-A53

2014-05-25T18:05:30+00:00

In order to allow KVM to run on Cortex-A53 implementations, wire the
minimal support required.

Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

ARM/ARM64: KVM: Add base for PSCI v0.2 emulation

2014-04-30T11:18:57+00:00

Currently, the in-kernel PSCI emulation provides PSCI v0.1 interface to
VCPUs. This patch extends current in-kernel PSCI emulation to provide
PSCI v0.2 interface to VCPUs.

By default, ARM/ARM64 KVM will always provide PSCI v0.1 interface for
keeping the ABI backward-compatible.

To select PSCI v0.2 interface for VCPUs, the user space (i.e. QEMU or
KVMTOOL) will have to set KVM_ARM_VCPU_PSCI_0_2 feature when doing VCPU
init using KVM_ARM_VCPU_INIT ioctl.

Signed-off-by: Anup Patel 
Signed-off-by: Pranavkumar Sawargaonkar 
Acked-by: Christoffer Dall 
Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

arm64: KVM: Add VGIC device control for arm64

2014-02-14T10:09:49+00:00

This fixes the build breakage introduced by
c07a0191ef2de1f9510f12d1f88e3b0b5cd8d66f and adds support for the device
control API and save/restore of the VGIC state for ARMv8.

The defines were simply missing from the arm64 header files and
uaccess.h must be implicitly imported from somewhere else on arm.

Signed-off-by: Christoffer Dall 
Signed-off-by: Paolo Bonzini

Merge branch 'kvm-arm64/for-3.14' into kvm-arm64/next

2013-12-28T10:29:37+00:00

arm64: KVM: Support X-Gene guest VCPU on APM X-Gene host

2013-12-28T10:28:50+00:00

This patch allows us to have X-Gene guest VCPU when using KVM arm64
on APM X-Gene host.

We add KVM_ARM_TARGET_XGENE_POTENZA for X-Gene Potenza compatible
guest VCPU and we return KVM_ARM_TARGET_XGENE_POTENZA in kvm_target_cpu()
when running on X-Gene host with Potenza core.

[maz: sanitized the commit log]

Signed-off-by: Anup Patel 
Signed-off-by: Pranavkumar Sawargaonkar 
Signed-off-by: Marc Zyngier

ARM/KVM: save and restore generic timer registers

2013-12-21T18:00:15+00:00

For migration to work we need to save (and later restore) the state of
each core's virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and export
the three needed registers (control, counter, compare value).
Though they live in cp15 space, we don't use the existing list, since
they need special accessor functions and the arch timer is optional.

Acked-by: Marc Zynger 
Signed-off-by: Andre Przywara 
Signed-off-by: Christoffer Dall

arm64: KVM: enable initialization of a 32bit vcpu

2013-06-12T15:42:18+00:00

Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
and providing sensible defaults out of reset state.

This feature is of course conditioned by the presence of 32bit
capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
capability.

Reviewed-by: Catalin Marinas 
Signed-off-by: Marc Zyngier

arm64: KVM: define 32bit specific registers

2013-06-12T15:42:13+00:00

Define the 32bit specific registers (SPSRs, cp15...).

Most CPU registers are directly mapped to a 64bit register
(r0->x0...). Only the SPSRs have separate registers.

cp15 registers are also mapped into their 64bit counterpart in most
cases.

Reviewed-by: Christopher Covington 
Reviewed-by: Catalin Marinas 
Signed-off-by: Marc Zyngier

arm64: KVM: PSCI implementation

2013-06-12T15:40:32+00:00

Wire the PSCI backend into the exit handling code.

Reviewed-by: Christopher Covington 
Reviewed-by: Catalin Marinas 
Signed-off-by: Marc Zyngier

arm64: KVM: system register handling

2013-06-07T13:03:36+00:00

Provide 64bit system register handling, modeled after the cp15
handling for ARM.

Reviewed-by: Christopher Covington 
Reviewed-by: Catalin Marinas 
Signed-off-by: Marc Zyngier