linux-toradex.git/arch/arm64/kernel/smp.c, branch v3.10.76

arm64: Fix up /proc/cpuinfo

2015-02-11T06:48:17+00:00

commit 44b82b7700d05a52cd983799d3ecde1a976b3bed upstream.

Commit d7a49086f263164a (arm64: cpuinfo: print info for all CPUs)
attempted to clean up /proc/cpuinfo, but due to concerns regarding
further changes was reverted in commit 5e39977edf6500fd (Revert "arm64:
cpuinfo: print info for all CPUs").

There are two major issues with the arm64 /proc/cpuinfo format
currently:

* The "Features" line describes (only) the 64-bit hwcaps, which is
  problematic for some 32-bit applications which attempt to parse it. As
  the same names are used for analogous ISA features (e.g. aes) despite
  these generally being architecturally unrelated, it is not possible to
  simply append the 64-bit and 32-bit hwcaps in a manner that might not
  be misleading to some applications.

  Various potential solutions have appeared in vendor kernels. Typically
  the format of the Features line varies depending on whether the task
  is 32-bit.

* Information is only printed regarding a single CPU. This does not
  match the ARM format, and does not provide sufficient information in
  big.LITTLE systems where CPUs are heterogeneous. The CPU information
  printed is queried from the current CPU's registers, which is racy
  w.r.t. cross-cpu migration.

This patch attempts to solve these issues. The following changes are
made:

* When a task with a LINUX32 personality attempts to read /proc/cpuinfo,
  the "Features" line contains the decoded 32-bit hwcaps, as with the
  arm port. Otherwise, the decoded 64-bit hwcaps are shown. This aligns
  with the behaviour of COMPAT_UTS_MACHINE and COMPAT_ELF_PLATFORM. In
  the absense of compat support, the Features line is empty.

  The set of hwcaps injected into a task's auxval are unaffected.

* Properties are printed per-cpu, as with the ARM port. The per-cpu
  information is queried from pre-recorded cpu information (as used by
  the sanity checks).

* As with the previous attempt at fixing up /proc/cpuinfo, the hardware
  field is removed. The only users so far are 32-bit applications tied
  to particular boards, so no portable applications should be affected,
  and this should prevent future tying to particular boards.

The following differences remain:

* No model_name is printed, as this cannot be queried from the hardware
  and cannot be provided in a stable fashion. Use of the CPU
  {implementor,variant,part,revision} fields is sufficient to identify a
  CPU and is portable across arm and arm64.

* The following system-wide properties are not provided, as they are not
  possible to provide generally. Programs relying on these are already
  tied to particular (32-bit only) boards:
  - Hardware
  - Revision
  - Serial

No software has yet been identified for which these remaining
differences are problematic.

Cc: Greg Hackmann 
Cc: Ian Campbell 
Cc: Serban Constantinescu 
Cc: Will Deacon 
Cc: cross-distro@lists.linaro.org
Cc: linux-api@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Catalin Marinas 
[Mark: backport to v3.10.x]
Signed-off-by: Mark Rutland 
Signed-off-by: Will Deacon 
Signed-off-by: Greg Kroah-Hartman

arm64: Only enable local interrupts after the CPU is marked online

2014-01-09T20:24:26+00:00

commit 53ae3acd4390ffeecb3a11dbd5be347b5a3d98f2 upstream.

There is a slight chance that (timer) interrupts are triggered before a
secondary CPU has been marked online with implications on softirq thread
affinity.

Signed-off-by: Catalin Marinas 
Reported-by: Kirill Tkhai 
Cc: Mark Brown 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

2013-04-30T17:10:48+00:00

Pull arm64 update from Catalin Marinas:
 "Main features:

   - Versatile Express SoC (model) support - DT files and Kconfig
     entries (there are no arch/arm64/mach-* directories).  The bulk of
     the code has already been moved to drivers/ as part of the ARM SoC
     clean-up.

   - Basic multi-cluster support (CPU logical map initialised from the
     DT)

   - Simple earlyprintk support for UART 8250/16550 and FastModel
     console output

   - Optimised kernel library bitops and string functions.

   - Automatic initialisation of the irqchip and clocks via DT"

* tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (26 commits)
  arm64: Use acquire/release semantics instead of explicit DMB
  arm64: klib: bitops: fix unpredictable stxr usage
  arm64: vexpress: Enable ARMv8 RTSM model (SoC) support
  arm64: vexpress: Add dts files for the ARMv8 RTSM models
  arm64: Survive invalid cpu enable-methods
  arm64: mm: Correct show_pte behaviour
  arm64: Fix compat types affecting struct compat_stat
  arm64: Execute DSB during thread switching for TLB/cache maintenance
  arm64: compiling issue, need add include/asm/vga.h file
  arm64: smp: honour #address-size when parsing CPU reg property
  arm64: Define cmpxchg64 and cmpxchg64_local for outside use
  arm64: Define readq and writeq for driver module using
  arm64: Fix task tracing
  arm64: add explicit symbols to ESR_EL1 decoding
  arm64: Use irqchip_init() for interrupt controller initialisation
  arm64: psci: Use the MPIDR values from cpu_logical_map for cpu ids.
  arm64: klib: Optimised atomic bitops
  arm64: klib: Optimised string functions
  arm64: klib: Optimised memory functions
  arm64: head: match all affinity levels in the pen of the secondaries
  ...

arm64: Survive invalid cpu enable-methods

2013-04-25T16:45:54+00:00

Currently, if you pass the kernel a dtb where a cpu node has an
unsupported enable-method property (e.g. "not-psci"), it'll explode
horribly, as it iterates over the enable_ops array incorrectly. It
increments the pointer *at* the current element, rather than
incrementing the pointer *to* the current element. As the first two
elements pointed to structures that were contiguous in memory, this
happened to be equivalent. However the third element is NULL, so when
the list is exhausted, smp_get_enable_ops generates the wrong pointer,
and dereferences an arbitrary portion of memory, which currently happens
to contain zero.

This patch fixes this by indirecting the pointer one level, so we
iterate over the array elements correctly, avoiding the below panic:

Signed-off-by: Mark Rutland 
Signed-off-by: Catalin Marinas

arm64: smp: honour #address-size when parsing CPU reg property

2013-04-25T16:45:43+00:00

For systems where the top 32-bits of the MPIDR are all zero, we should
allow the device-tree to specify an #address-size of 0x1 for the CPU reg
property and then zero extend the value there.

Without this patch, kvmtool breaks with the recent mpidr parsing code
introduced in 4c7aa0021356 ("arm64: kernel: initialise cpu_logical_map
from the DT").

Acked-by: Javi Merino 
Acked-by: Lorenzo Pieralisi 
Signed-off-by: Will Deacon 
Signed-off-by: Catalin Marinas

arm64: Use generic idle loop

2013-04-08T15:39:24+00:00

Signed-off-by: Thomas Gleixner 
Cc: Linus Torvalds 
Cc: Rusty Russell 
Cc: Paul McKenney 
Cc: Peter Zijlstra 
Reviewed-by: Cc: Srivatsa S. Bhat 
Cc: Magnus Damm 
Acked-by: Catalin Marinas 
Link: http://lkml.kernel.org/r/20130321215233.887563095@linutronix.de

arm64: kernel: initialise cpu_logical_map from the DT

2013-03-20T17:26:24+00:00

When booting the kernel, the cpu logical id map must be initialised
using device tree data passed by FW or through an embedded blob.

This patch parses the reg property in device tree "cpu" nodes,
retrieves the corresponding CPUs hardware identifiers (MPIDR) and
initialises the cpu logical map accordingly.

The device tree HW identifiers are considered valid if all CPU nodes
contain a "reg" property, there are no duplicate "reg" entries and the
DT defines a CPU node whose "reg" property defines affinity levels
that matches those of the boot CPU.

The primary CPU is assigned cpu logical number 0 to keep the current
convention valid.

Based on a0ae02405076ac32bd17ece976e914b5b6075bb0 (ARM: kernel: add
device tree init map function).

Signed-off-by: Javi Merino 
Signed-off-by: Catalin Marinas

arm64: kernel: make the pen of the secondary a 64-bit unsigned value

2013-03-20T17:22:12+00:00

Change the prototype of write_pen_release() accordingly and clarify
that's holding the hardware id of the secondary that's going to boot.
This is in preparation of getting HWIDs parsed from the DT.

Signed-off-by: Javi Merino 
Signed-off-by: Catalin Marinas

arm64: SMP: enable PSCI boot method

2013-01-29T16:56:37+00:00

Wire the PSCI implementation into the SMP secondary startup
code.

Signed-off-by: Marc Zyngier 
Signed-off-by: Catalin Marinas

arm64: SMP: rework the SMP code to be enabling method agnostic

2013-01-29T16:56:37+00:00

In order to introduce PSCI support, let the SMP code handle
multiple enabling methods. This also allow CPUs to be booted
using different methods (though this feels a bit weird...).

In the process, move the spin-table code to its own file.

Signed-off-by: Marc Zyngier 
Signed-off-by: Catalin Marinas