linux-toradex.git/arch/arm64/lib/bitops.S, branch v3.10.76 Linux kernel for Apalis and Colibri modules arm64: Treat the bitops index argument as an 'int' 2013-05-08T09:33:17+00:00 Catalin Marinas catalin.marinas@arm.com 2013-05-07T17:02:58+00:00 420c158dcf96ee3a5758c9bf1586b163584c75c7 The bitops prototype use an 'int' as the bit index type but the asm implementation assume it to be a 'long'. Since the compiler does not guarantee zeroing the upper 32-bits in a register when used as 'int', change the bitops implementation accordingly. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
The bitops prototype use an 'int' as the bit index type but the asm
implementation assume it to be a 'long'. Since the compiler does not
guarantee zeroing the upper 32-bits in a register when used as 'int',
change the bitops implementation accordingly.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: Use acquire/release semantics instead of explicit DMB 2013-04-30T14:58:37+00:00 Catalin Marinas catalin.marinas@arm.com 2013-04-30T14:58:37+00:00 16c85a1fd73eade2ae290d759924c09b4595f504 This patch changes the test_and_*_bit functions to use the load-acquire/store-release instructions instead of explicit DMB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
This patch changes the test_and_*_bit functions to use the
load-acquire/store-release instructions instead of explicit DMB.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: klib: bitops: fix unpredictable stxr usage 2013-04-30T14:53:01+00:00 Mark Rutland mark.rutland@arm.com 2013-04-30T10:11:15+00:00 c47d6a04e6ed22ccc5d89aaf2a136bf4971de310 We're currently relying on unpredictable behaviour in our testops (test_and_*_bit), as stxr is unpredictable when the status register and the source register are the same This patch changes reallocates the status register so as to bring us back into the realm of predictable behaviour. Boot tested on an AEMv8 model. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
We're currently relying on unpredictable behaviour in our testops
(test_and_*_bit), as stxr is unpredictable when the status register and
the source register are the same

This patch changes reallocates the status register so as to bring us back into
the realm of predictable behaviour. Boot tested on an AEMv8 model.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: klib: Optimised atomic bitops 2013-03-21T17:39:31+00:00 Catalin Marinas catalin.marinas@arm.com 2013-03-21T16:28:47+00:00 62479586532715b6da4777374a6f53b32453385e This patch implements the AArch64-specific atomic bitops functions using exclusive memory accesses to avoid locking. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
This patch implements the AArch64-specific atomic bitops functions using
exclusive memory accesses to avoid locking.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>