linux-toradex.git/arch/arm, branch v3.10.37

ARM: highbank: avoid L2 cache smc calls when PL310 is not present

2014-03-31T16:58:13+00:00

commit a56a5cf1f2ec895599eace0ac6eba1e4a489e4bf upstream.

While Midway firmware handles L2 smc calls as nops, the custom smc calls
present a problem when running virtualized Midway guest. They aren't
needed so just avoid calling them.

In the process, cleanup the L2X0 ifdefs and use IS_ENABLED instead.

Signed-off-by: Rob Herring 
Signed-off-by: Ian Campbell 
Signed-off-by: Greg Kroah-Hartman

ARM: move outer_cache declaration out of ifdef

2014-03-31T16:58:13+00:00

commit 0b53c11d533a8f6688d73fad0baf67dd08ec1b90 upstream.

Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that
outer_cache can be used inside IS_ENABLED condition.

Signed-off-by: Rob Herring 
Cc: Russell King 
Signed-off-by: Ian Campbell 
Signed-off-by: Greg Kroah-Hartman

ARM: ignore memory below PHYS_OFFSET

2014-03-24T04:38:21+00:00

commit 571b14375019c3a66ef70d4d4a7083f4238aca30 upstream.

If the kernel is loaded higher in physical memory than normal, and we
calculate PHYS_OFFSET higher than the start of RAM, this leads to
boot problems as we attempt to map part of this RAM into userspace.
Rather than struggle with this, just truncate the mapping.

Signed-off-by: Russell King 
Cc: Wang Nan 
Signed-off-by: Greg Kroah-Hartman

ARM: 7864/1: Handle 64-bit memory in case of 32-bit phys_addr_t

2014-03-24T04:38:21+00:00

commit 6d7d5da7d75c6df676c8b72d32b02ff024438f0c upstream.

Use CONFIG_ARCH_PHYS_ADDR_T_64BIT to determine
if ignoring or truncating of memory banks is
neccessary. This may be needed in the case of
64-bit memory bank addresses but when phys_addr_t
is kept 32-bit.

Signed-off-by: Magnus Damm 
Signed-off-by: Russell King 
Cc: Wang Nan 
Signed-off-by: Greg Kroah-Hartman

ARM: 7991/1: sa1100: fix compile problem on Collie

2014-03-24T04:38:14+00:00

commit 052450fdc55894a39fbae93d9bbe43947956f663 upstream.

Due to a problem in the MFD Kconfig it was not possible to
compile the UCB battery driver for the Collie SA1100 system,
in turn making it impossible to compile in the battery driver.
(See patch "mfd: include all drivers in subsystem menu".)

After fixing the MFD Kconfig (separate patch) a compile error
appears in the Collie battery driver due to the 
implicitly requiring  through 
via  prior to commit
40ca061b "ARM: 7841/1: sa1100: remove complex GPIO interface".

Fix this up by including the required header into
.

Cc: Andrea Adami 
Cc: Dmitry Eremin-Solenikov 
Signed-off-by: Linus Walleij 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

ARM: 7811/1: locks: use early clobber in arch_spin_trylock

2014-03-24T04:38:13+00:00

commit afa31d8eb86fc2f25083e675d57ac8173a98f999 upstream.

The res variable is written before we've finished with the input
operands (namely the lock address), so ensure that we mark it as `early
clobber' to avoid unintended register sharing.

Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
Cc: Wang Weidong 
Signed-off-by: Greg Kroah-Hartman

ARM: 7812/1: rwlocks: retry trylock operation if strex fails on free lock

2014-03-07T05:30:13+00:00

commit 00efaa0250939dc148e2d3104fb3c18395d24a2d upstream.

Commit 15e7e5c1ebf5 ("ARM: 7749/1: spinlock: retry trylock operation if
strex fails on free lock") modifying our arch_spin_trylock to retry the
acquisition if the lock appeared uncontended, but the strex failed.

This patch does the same for rwlocks, which were missed by the original
patch.

Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
Cc: Li Zefan 
Signed-off-by: Greg Kroah-Hartman

ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock

2014-03-07T05:30:13+00:00

commit 15e7e5c1ebf556cd620c9b091e121091ac760f6d upstream.

An exclusive store instruction may fail for reasons other than lock
contention (e.g. a cache eviction during the critical section) so, in
line with other architectures using similar exclusive instructions
(alpha, mips, powerpc), retry the trylock operation if the lock appears
to be free but the strex reported failure.

Reported-by: Tony Thompson 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
Cc: Li Zefan 
Signed-off-by: Greg Kroah-Hartman

ARM: tegra: only run PL310 init on systems with one

2014-03-07T05:30:12+00:00

commit 8859685785bfafadf9bc922dd3a2278e59886947 upstream.

Fix tegra_init_cache() to check whether the system has a PL310 cache
before touching the PL310 registers. This prevents access to non-existent
registers on Tegra114 and later.

Note for stable kernels:
In <= v3.12, the file to patch is arch/arm/mach-tegra/common.c.

Signed-off-by: Stephen Warren 
Signed-off-by: Olof Johansson 
Signed-off-by: Greg Kroah-Hartman

ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module

2014-03-07T05:30:01+00:00

commit 980386d2d6d49e0b42f48550853ef1ad6aa5d79a upstream.

Fixes: commit 75d3625e0e86b2d8d77b4e9c6f685fd7ea0d5a96
       ARM: OMAP2+: gpmc: add DT bindings for OneNAND

OMAP SoC(s) depend on GPMC controller driver to parse GPMC DT child nodes and
register them platform_device for ONENAND driver to probe later. However this does
not happen if generic MTD_ONENAND framework is built as module (CONFIG_MTD_ONENAND=m).

Therefore, when MTD/ONENAND and MTD/ONENAND/OMAP2 modules are loaded, they are unable
to find any matching platform_device and remain un-binded. This causes on board
ONENAND flash to remain un-detected.

This patch causes GPMC controller to parse DT nodes when
CONFIG_MTD_ONENAND=y || CONFIG_MTD_ONENAND=m

Signed-off-by: Pekon Gupta 
Signed-off-by: Tony Lindgren 
Signed-off-by: Greg Kroah-Hartman