linux-toradex.git/arch/arm, branch v3.4.18

Revert: ARM: SAMSUNG: Add naming of s3c64xx-spi devices

2012-11-05T08:50:42+00:00

This reverts commit baa526f45d3f096a1cd9f14b668203a03bbab6f9, which is 
commit 308b3afb97dc342e9c4f958d8b4c459ae0e22bd7 upstream.

To quote Colin Cross:
	This patch breaks Exynos5 spi on 3.4.17.  The patch with the bug
	that this patch was supposed to address went in to 3.6 and not
	3.4, so this patch causes a driver name mismatch when applied to
	3.4.


Cc: Colin Cross 
Cc: Heiko Stuebner 
Cc: Sylwester Nawrocki 
Cc: Kukjin Kim 
Signed-off-by: Greg Kroah-Hartman

ARM: at91: at91sam9g10: fix SOC type detection

2012-10-31T17:03:01+00:00

commit 3d9a0183dd3423353e9e363bcc261c1220d05f9f upstream.

Newer at91sam9g10 SoC revision can't be detected, so the kernel can't boot with
this kind of kernel panic:
"AT91: Impossible to detect the SOC type"

CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Atmel AT91SAM9G10-EK
Ignoring tag cmdline (using the default kernel command line)
bootconsole [earlycon0] enabled
Memory policy: ECC disabled, Data cache writeback
Kernel panic - not syncing: AT91: Impossible to detect the SOC type
[] (unwind_backtrace+0x0/0xe0) from [] (panic+0x78/0x1cc)
[] (panic+0x78/0x1cc) from [] (at91_map_io+0x90/0xc8)
[] (at91_map_io+0x90/0xc8) from [] (paging_init+0x564/0x6d0)
[] (paging_init+0x564/0x6d0) from [] (setup_arch+0x464/0x704)
[] (setup_arch+0x464/0x704) from [] (start_kernel+0x6c/0x2d4)
[] (start_kernel+0x6c/0x2d4) from [<20008040>] (0x20008040)

The reason for this is that the Debug Unit Chip ID Register has changed between
Engineering Sample and definitive revision of the SoC. Changing the check of
cidr to socid will address the problem. We do not integrate this check to the
list just above because we also have to make sure that the extended id is
disregarded.

Signed-off-by: Ivan Shugov 
[nicolas.ferre@atmel.com: change commit message]
Signed-off-by: Nicolas Ferre 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD 
Signed-off-by: Greg Kroah-Hartman

ARM: at91/i2c: change id to let i2c-gpio work

2012-10-31T17:03:01+00:00

commit 7840487cd6298f9f931103b558290d8d98d41c49 upstream.

The i2c core driver will turn the platform device ID to busnum
When using platfrom device ID as -1, it means dynamically assigned
the busnum. When writing code, we need to make sure the busnum,
and call i2c_register_board_info(int busnum, ...) to register device
if using -1, we do not know the value of busnum

In order to solve this issue, set the platform device ID as a fix number
Here using 0 to match the busnum used in i2c_regsiter_board_info()

Signed-off-by: Bo Shen 
Acked-by: Jean Delvare 
Signed-off-by: Nicolas Ferre 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD 
Acked-by: Ludovic Desroches 
Signed-off-by: Greg Kroah-Hartman

ARM: SAMSUNG: Add naming of s3c64xx-spi devices

2012-10-31T17:03:01+00:00

commit 308b3afb97dc342e9c4f958d8b4c459ae0e22bd7 upstream.

Commit a5238e360b71 (spi: s3c64xx: move controller information into driver
data) introduced separate device names for the different subtypes of the
spi controller but forgot to set these in the relevant machines.

To fix this introduce a s3c64xx_spi_setname function and populate all
Samsung arches with the correct names. The function resides in a new
header, as the s3c64xx-spi.h contains driver platform data and should
therefore at some later point move out of the Samsung include dir.

Tested on a s3c2416-based machine.

Signed-off-by: Heiko Stuebner 
Reviewed-by: Sylwester Nawrocki 
[s.nawrocki@samsung.com: tested on mach-exynos]
Tested-by: Sylwester Nawrocki 
Signed-off-by: Kukjin Kim 
Signed-off-by: Greg Kroah-Hartman

ARM: 7559/1: smp: switch away from the idmap before updating init_mm.mm_count

2012-10-31T17:02:56+00:00

commit 5f40b909728ad784eb43aa309d3c4e9bdf050781 upstream.

When booting a secondary CPU, the primary CPU hands two sets of page
tables via the secondary_data struct:

	(1) swapper_pg_dir: a normal, cacheable, shared (if SMP) mapping
	    of the kernel image (i.e. the tables used by init_mm).

	(2) idmap_pgd: an uncached mapping of the .idmap.text ELF
	    section.

The idmap is generally used when enabling and disabling the MMU, which
includes early CPU boot. In this case, the secondary CPU switches to
swapper as soon as it enters C code:

	struct mm_struct *mm = &init_mm;
	unsigned int cpu = smp_processor_id();

	/*
	 * All kernel threads share the same mm context; grab a
	 * reference and switch to it.
	 */
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;
	cpumask_set_cpu(cpu, mm_cpumask(mm));
	cpu_switch_mm(mm->pgd, mm);

This causes a problem on ARMv7, where the identity mapping is treated as
strongly-ordered leading to architecturally UNPREDICTABLE behaviour of
exclusive accesses, such as those used by atomic_inc.

This patch re-orders the secondary_start_kernel function so that we
switch to swapper before performing any exclusive accesses.

Reported-by: Gilles Chanteperdrix 
Cc: David McKay 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

ARM: 7541/1: Add ARM ERRATA 775420 workaround

2012-10-21T16:27:58+00:00

commit 7253b85cc62d6ff84143d96fe6cd54f73736f4d7 upstream.

arm: Add ARM ERRATA 775420 workaround

Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.

Based on work by Kouei Abe and feedback from Catalin Marinas.

Signed-off-by: Kouei Abe 
[ horms@verge.net.au: Changed to implementation
  suggested by catalin.marinas@arm.com ]
Acked-by: Catalin Marinas 
Signed-off-by: Simon Horman 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

ARM: vfp: fix saving d16-d31 vfp registers on v6+ kernels

2012-10-21T16:27:57+00:00

commit 846a136881b8f73c1f74250bf6acfaa309cab1f2 upstream.

Michael Olbrich reported that his test program fails when built with
-O2 -mcpu=cortex-a8 -mfpu=neon, and a kernel which supports v6 and v7
CPUs:

volatile int x = 2;
volatile int64_t y = 2;

int main() {
	volatile int a = 0;
	volatile int64_t b = 0;
	while (1) {
		a = (a + x) % (1 << 30);
		b = (b + y) % (1 << 30);
		assert(a == b);
	}
}

and two instances are run.  When built for just v7 CPUs, this program
works fine.  It uses the "vadd.i64 d19, d18, d16" VFP instruction.

It appears that we do not save the high-16 double VFP registers across
context switches when the kernel is built for v6 CPUs.  Fix that.

Tested-By: Michael Olbrich 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

serial: omap: fix software flow control

2012-10-07T15:32:25+00:00

commit 957ee7270d632245b43f6feb0e70d9a5e9ea6cf6 upstream.

Software flow control register bits were not defined correctly.

Also clarify the IXON and IXOFF logic to reflect what userspace wants.

Tested-by: Shubhrajyoti D 
Signed-off-by: Vikram Pandita 
Signed-off-by: Shubhrajyoti D 
Acked-by: Tony Lindgren 
Signed-off-by: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman

ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+

2012-10-02T17:30:49+00:00

commit a76d7bd96d65fa5119adba97e1b58d95f2e78829 upstream.

The open-coded mutex implementation for ARMv6+ cores suffers from a
severe lack of barriers, so in the uncontended case we don't actually
protect any accesses performed during the critical section.

Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec
code but optimised to remove a branch instruction, as the mutex fastpath
was previously inlined. Now that this is executed out-of-line, we can
reuse the atomic access code for the locking (in fact, we use the xchg
code as this produces shorter critical sections).

This patch uses the generic xchg based implementation for mutexes on
ARMv6+, which introduces barriers to the lock/unlock operations and also
has the benefit of removing a fair amount of inline assembly code.

Acked-by: Arnd Bergmann 
Acked-by: Nicolas Pitre 
Reported-by: Shan Kang 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 cores

2012-10-02T17:30:08+00:00

commit e1e5b7e4251c7538ca08c2c5545b0c2fbd8a6635 upstream.

This patch zeroes the SCTLR.TRE bit prior to setting the mapping as
cacheable for ARMv7 cores in the decompressor, ensuring that the
memory region attributes are obtained from the C and B bits, not from
the page tables.

Cc: Nicolas Pitre 
Reviewed-by: Will Deacon 
Signed-off-by: Matthew Leach 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman