linux-toradex.git/arch/blackfin/Kconfig, branch v3.2.4

Blackfin: drop unused Kconfig symbol

2011-10-25T23:51:59+00:00

Signed-off-by: Paul Bolle 
Signed-off-by: Mike Frysinger

Blackfin: pwm: implement linux/pwm.h API

2011-07-23T05:18:23+00:00

For now, this only supports gptimers.  Support for dedicated PWM devices
as found on newer parts to come.

Signed-off-by: Michael Hennerich 
Signed-off-by: Mike Frysinger

arch: remove CONFIG_GENERIC_FIND_{NEXT_BIT,BIT_LE,LAST_BIT}

2011-05-27T00:12:38+00:00

By the previous style change, CONFIG_GENERIC_FIND_NEXT_BIT,
CONFIG_GENERIC_FIND_BIT_LE, and CONFIG_GENERIC_FIND_LAST_BIT are not used
to test for existence of find bitops anymore.

Signed-off-by: Akinobu Mita 
Acked-by: Greg Ungerer 
Cc: Arnd Bergmann 
Cc: Russell King 
Cc: Martin Schwidefsky 
Cc: Heiko Carstens 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Blackfin: initial perf_event support

2011-05-25T12:24:09+00:00

Signed-off-by: Mike Frysinger

genirq: Remove the now obsolete config options and select statements

2011-03-30T12:13:23+00:00

Signed-off-by: Thomas Gleixner

Blackfin: enable atomic64_t support

2011-03-23T01:03:17+00:00

Signed-off-by: Mike Frysinger

Blackfin: enable GENERIC_HARDIRQS_NO_DEPRECATED

2011-03-18T08:01:09+00:00

All chips converted.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Mike Frysinger

Blackfin: SMP: work around anomaly 05000491

2011-03-18T08:01:04+00:00

In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram.  The trouble with multi-core systems is that all
L1 sram is visible only to the active core.  So we can't just place the
functions into L1 and call it directly.  We need to setup a jump table and
place the entry point in external memory.  This will call the right func
based on the active core.

In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.

Signed-off-by: Sonic Zhang 
Signed-off-by: Mike Frysinger

Blackfin: split optimization settings more

2011-03-18T08:01:03+00:00

We need to place icache flush funcs into L1 inst sram to work around a
hardware anomaly.  But this currently breaks SMP support as the L1 inst
sram is per-core and cannot be called directly.  So in preparation for
making that work, split the two options.

Further, split out the SMP depend so that we can allow some for SMP.

Signed-off-by: Mike Frysinger

blackfin: Use generic irq Kconfig

2011-01-21T10:55:31+00:00

No functional change.

Signed-off-by: Thomas Gleixner 
Cc: Mike Frysinger