Back in commit c03c2a87347b849ec927d, we fixed logic in the non-bf54x
GPIO resume code to set the data levels properly before the direction
to avoid spurious line glitches.  But we missed the bf54x code paths.
So add the same fix there.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Re-architect how we save/restore the gpio/port logic that only pertains
to bf538/bf539 parts by pulling it out of the core code paths and pushing
it out to bf538-specific locations.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

->read_proc interface is going away, switch to seq_file.

Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The BF537 SIC combines the gpio port H mask A interrupts with the
emac rx interrupt, so we need to demux this in software.

It also combines the gpio port H mask B and the emac tx interrupts,
and the watchdog and port F mask B interrupts, but since we don't
support mask B yet, just add the defines for now.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

These are only used in a few internal Blackfin places, so move the irq
prototypes out of the global header and into the internal irq one.  No
functional changes other than shuffling locales.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Many Blackfin parts group sets of pins into a single functional unit.
This means you cannot use different pins within a group for different
peripherals.  Our resource conflict checking thus far has been limited
to individual pins, so if someone tried to grab a different pin from
the same group, it would be allowed while silently changing the other
pins in the same group.

One common example is the pin set PG12 - PG15 on BF51x parts.  They
may either be used with SPI0 (1st function), or they may be used with
PTP/PWM/AMS3 (3rd function).  Ideally, we'd like to use PG12 - PG14
for SPI0 while using PG15 with AMS3, but the hardware does not permit
this.  In the past, the software would allow the pins to be requested
this way, but ultimately things like the Blackfin SPI driver would
stop working when the hardware rerouted to a different peripheral.

Signed-off-by: steven miao <realmz6@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Rename h/w IRQ flags handling functions to be in line with what is expected for
the irq renaming patch.  This renames local_*_hw() to hard_local_*() using the
following perl command:

	perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"`

and then fixing up asm/irqflags.h manually.

Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both
return the flags rather than passing it through the argument list.

Signed-off-by: David Howells <dhowells@redhat.com>

Some processors have groups of pins that aren't an even number of 16.
This causes the array size calculation to under count the number of
needed entries due to integer truncation.  So on the BF51x, while we
should have 3 bitmaps (41 / 16), we end up with 2 and pin requests for
the 3rd bank end up scribbling over the top of the GPIO IRQ array.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Random tabs instead of spaces, mixes of the two, and unicode spaces
instead of ascii spaces.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The duplicated bit banging logic is getting out of hand, so unify the
local API to make management a lot easier.  This also makes the code
a lot easier to follow.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>