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<title>linux-toradex.git/arch/c6x/platforms/plldata.c, branch v3.17</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>C6X: add basic support for TMS320C6678 SoC</title>
<updated>2012-07-19T03:52:31+00:00</updated>
<author>
<name>Ken Cox</name>
<email>jkc@redhat.com</email>
</author>
<published>2012-07-19T03:19:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=dbe91a2e6e53aa85efa0aac86e3a22ba95f8b85f'/>
<id>dbe91a2e6e53aa85efa0aac86e3a22ba95f8b85f</id>
<content type='text'>
This patch adds support for the TMS320C6678 SoC on an EVMC6678LE
evaluation board. The 6678 is a C66x family CPU which is very similar
to the already supported C64x CPUs with the addition of floating point
instructions.

Signed-off-by: Ken Cox &lt;jkc@redhat.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
CC: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
CC: linux-c6x-dev@linux-c6x.org
</content>
<content type='xhtml'>
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<pre>
This patch adds support for the TMS320C6678 SoC on an EVMC6678LE
evaluation board. The 6678 is a C66x family CPU which is very similar
to the already supported C64x CPUs with the addition of floating point
instructions.

Signed-off-by: Ken Cox &lt;jkc@redhat.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
CC: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
CC: linux-c6x-dev@linux-c6x.org
</pre>
</div>
</content>
</entry>
<entry>
<title>C6X: clocks</title>
<updated>2011-10-06T23:48:07+00:00</updated>
<author>
<name>Mark Salter</name>
<email>msalter@redhat.com</email>
</author>
<published>2011-10-04T15:10:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=81ec98898188639ac53413605681b3e3bb0a2ff1'/>
<id>81ec98898188639ac53413605681b3e3bb0a2ff1</id>
<content type='text'>
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs
feeding into the cores or peripheral clock domains. The hardware is very similar
to arm/mach-davinci clocks. This is still a work in progress which needs to be
updated once device tree clock binding changes shake out.

Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
Signed-off-by: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs
feeding into the cores or peripheral clock domains. The hardware is very similar
to arm/mach-davinci clocks. This is still a work in progress which needs to be
updated once device tree clock binding changes shake out.

Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
Signed-off-by: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</pre>
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</content>
</entry>
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