<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/c6x/platforms/timer64.c, branch v3.4.23</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Disintegrate asm/system.h for C6X</title>
<updated>2012-03-28T17:30:02+00:00</updated>
<author>
<name>David Howells</name>
<email>dhowells@redhat.com</email>
</author>
<published>2012-03-28T17:30:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=6a846f3f821a252762897751fa0aeb68dda635f5'/>
<id>6a846f3f821a252762897751fa0aeb68dda635f5</id>
<content type='text'>
Disintegrate asm/system.h for C6X.

Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
cc: linux-c6x-dev@linux-c6x.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Disintegrate asm/system.h for C6X.

Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
cc: linux-c6x-dev@linux-c6x.org
</pre>
</div>
</content>
</entry>
<entry>
<title>C6X: fix timer64 initialization</title>
<updated>2012-01-08T20:12:17+00:00</updated>
<author>
<name>Mark Salter</name>
<email>msalter@redhat.com</email>
</author>
<published>2011-11-05T14:57:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=25b48ff852e2e71b0d44d8ee6f69c9b704bd5070'/>
<id>25b48ff852e2e71b0d44d8ee6f69c9b704bd5070</id>
<content type='text'>
Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.

Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.

Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>C6X: time management</title>
<updated>2011-10-06T23:47:51+00:00</updated>
<author>
<name>Aurelien Jacquiot</name>
<email>a-jacquiot@ti.com</email>
</author>
<published>2011-10-04T15:05:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=546a39546c64ad7e73796c5508ef5487af42cae2'/>
<id>546a39546c64ad7e73796c5508ef5487af42cae2</id>
<content type='text'>
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter &lt;msalter@redhat.com&gt;

Signed-off-by: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter &lt;msalter@redhat.com&gt;

Signed-off-by: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</pre>
</div>
</content>
</entry>
</feed>
