linux-toradex.git/arch/c6x/platforms, branch v3.4.2

Disintegrate asm/system.h for C6X

2012-03-28T17:30:02+00:00

Disintegrate asm/system.h for C6X.

Signed-off-by: David Howells 
Signed-off-by: Mark Salter 
cc: linux-c6x-dev@linux-c6x.org

irq_domain/c6x: Use library of xlate functions

2012-02-16T13:11:24+00:00

The c6x irq controllers don't need to define custom .xlate hooks

Signed-off-by: Grant Likely 
Cc: Rob Herring 
Cc: Mark Salter 
Cc: Thomas Gleixner

irq_domain/c6x: constify irq_domain structures

2012-02-16T13:11:24+00:00

Signed-off-by: Grant Likely 
Cc: Mark Salter 
Cc: Thomas Gleixner

irq_domain/c6x: Convert c6x to use generic irq_domain support.

2012-02-16T13:11:24+00:00

The C6X IRQ support was copied almost verbatim from the PowerPC virtual IRQ
code. The PowerPC code was used as the basis for generic irq_domain support,
so this patch mostly copies what what done to arch/powerpc by Grant Likely
in his irq_domain patch series.

Signed-off-by: Mark Salter 
Signed-off-by: Grant Likely 
Cc: Aurelien Jacquiot 
Cc: Thomas Gleixner

C6X: fix timer64 initialization

2012-01-08T20:12:17+00:00

Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.

Signed-off-by: Mark Salter

C6X: fix layout of EMIFA registers

2012-01-08T20:12:09+00:00

Signed-off-by: Mark Salter

C6X: DSCR - Device State Configuration Registers

2011-10-06T23:48:36+00:00

All SoCs provide an area of device configuration registers called the DSCR. The
location of specific registers as well as their use varies considerably from
implementation to implementation. Rather than having to rely on additional
SoC-specific DSCR code for each new supported SoC, this code generalize things
as much as possible using device tree properties. Initialization must take
place early on (setup_arch time) in case the event timer device needs to be
enable via the DSCR.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann

C6X: EMIF - External Memory Interface

2011-10-06T23:48:29+00:00

Several SoC parts provide a simple bridge to support external memory mapped
devices. This code probes the device tree for an EMIF node and sets up the
bridge registers if such a node is found. Beyond initial set up, there is no
further need to access the bridge control registers. External devices on the
bus are accessed through their MMIO registers using suitable drivers. The
bridge hardware does provide for timeout and other error interrupts, but these
are not yet supported.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann

C6X: cache control

2011-10-06T23:48:10+00:00

Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter 

Signed-off-by: Aurelien Jacquiot 
Signed-off-by: Mark Salter 
Acked-by: Arnd Bergmann

C6X: clocks

2011-10-06T23:48:07+00:00

The C6X SoCs contain several PLL controllers each with up to 16 clock outputs
feeding into the cores or peripheral clock domains. The hardware is very similar
to arm/mach-davinci clocks. This is still a work in progress which needs to be
updated once device tree clock binding changes shake out.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann