linux-toradex.git/arch/csky/mm/cachev2.c, branch v6.7 Linux kernel for Apalis and Colibri modules csky/ftrace: Fixup ftrace_modify_code deadlock without CPU_HAS_ICACHE_INS 2020-03-31T14:15:42+00:00 Guo Ren guoren@linux.alibaba.com 2020-03-31T14:15:42+00:00 dd7c983e78a28ff0b22f8bcf32a303b4f79cb318 If ICACHE_INS is not supported, we use IPI to sync icache on each core. But ftrace_modify_code is called from stop_machine from default implementation of arch_ftrace_update_code and stop_machine callback is irq_disabled. When you call ipi with irq_disabled, a deadlock will happen. We couldn't use icache_flush with irq_disabled, but startup make_nop is specific case and it needn't ipi other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> 
If ICACHE_INS is not supported, we use IPI to sync icache on each
core. But ftrace_modify_code is called from stop_machine from default
implementation of arch_ftrace_update_code and stop_machine callback
is irq_disabled. When you call ipi with irq_disabled, a deadlock will
happen.

We couldn't use icache_flush with irq_disabled, but startup make_nop
is specific case and it needn't ipi other cores.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
csky: Remove unused cache implementation 2020-02-21T07:43:25+00:00 Guo Ren guoren@linux.alibaba.com 2020-02-02T02:58:38+00:00 9025fd48a8aeddade845afa353d4bbab7f19dbf2 Only for coding convention, these codes are unnecessary for abiv2. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> 
Only for coding convention, these codes are unnecessary for abiv2.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
csky: Support icache flush without specific instructions 2020-02-21T07:43:24+00:00 Guo Ren guoren@linux.alibaba.com 2020-01-22T03:15:14+00:00 761b4f694cb90b63ca2739ac8a8a176342636e5e Some CPUs don't support icache specific instructions to flush icache lines in broadcast way. We use cpu control registers to flush local icache and use IPI to notify other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> 
Some CPUs don't support icache specific instructions to flush icache
lines in broadcast way. We use cpu control registers to flush local
icache and use IPI to notify other cores.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range 2019-08-06T07:15:34+00:00 Guo Ren ren_guo@c-sky.com 2019-07-30T09:16:28+00:00 ae76f635d4e1cffa6870cc5472567ca9d6940a22 DMA_FROM_DEVICE only need to read dma data of memory into CPU cache, so there is no need to clear cache before. Also clear + inv for DMA_FROM_DEVICE won't cause problem, because the memory range for dma won't be touched by software during dma working. Changes for V2: - Remove clr cache and ignore the DMA_TO_DEVICE in _for_cpu. - Change inv to wbinv cache with DMA_FROM_DEVICE in _for_device. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de> 
DMA_FROM_DEVICE only need to read dma data of memory into CPU cache,
so there is no need to clear cache before. Also clear + inv for
DMA_FROM_DEVICE won't cause problem, because the memory range for dma
won't be touched by software during dma working.

Changes for V2:
 - Remove clr cache and ignore the DMA_TO_DEVICE in _for_cpu.
 - Change inv to wbinv cache with DMA_FROM_DEVICE in _for_device.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
csky: Cache and TLB routines 2018-10-25T15:36:19+00:00 Guo Ren ren_guo@c-sky.com 2018-09-05T06:25:10+00:00 00a9730e1007c6cc87a7c78af2f24a4105d616ee This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 
This patch adds cache and tlb sync codes for abiv1 & abiv2.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>