<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/m68k/include/asm/mcfintc.h, branch v3.8.2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>m68knommu: map ColdFire interrupts to correct masking bits</title>
<updated>2009-09-15T23:43:52+00:00</updated>
<author>
<name>Greg Ungerer</name>
<email>gerg@uclinux.org</email>
</author>
<published>2009-05-22T03:33:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=39f0fb6a3448cfc316e0d5295ed1b121db50037e'/>
<id>39f0fb6a3448cfc316e0d5295ed1b121db50037e</id>
<content type='text'>
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>m68knommu: merge old ColdFire interrupt controller masking macros</title>
<updated>2009-09-15T23:43:50+00:00</updated>
<author>
<name>Greg Ungerer</name>
<email>gerg@uclinux.org</email>
</author>
<published>2009-05-19T04:38:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f2154bef817ac3d0ea67b52526fd8e88898b66f9'/>
<id>f2154bef817ac3d0ea67b52526fd8e88898b66f9</id>
<content type='text'>
Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>m68knommu: move ColdFire INTC definitions to new include file</title>
<updated>2009-09-15T23:43:49+00:00</updated>
<author>
<name>Greg Ungerer</name>
<email>gerg@uclinux.org</email>
</author>
<published>2009-05-19T03:56:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=5938084bd8843490a4493d19fb108df70d87df2d'/>
<id>5938084bd8843490a4493d19fb108df70d87df2d</id>
<content type='text'>
Create an mcfintc.h include file with the definitions for the old style
ColdFire interrupt controller. They are only needed on CPU's that use
this old controller - so isolate them on their own.

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Create an mcfintc.h include file with the definitions for the old style
ColdFire interrupt controller. They are only needed on CPU's that use
this old controller - so isolate them on their own.

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
