linux-toradex.git/arch/microblaze/kernel/hw_exception_handler.S, branch tegra-next

microblaze: Fix unaligned value saving to the stack for system with MMU

2011-07-25T07:07:45+00:00

Several registers weren't saved correctly to the stack.

Unaligned expection for system with MMU stores
value in ex_tmp_data_loc_X address which is load to registers r3.
The next step is to move this value from r3 to a destination
register which caused unaligned exception. For several registers
this value was directly moved to the register.

For example for r28:
by "or r28, r0, r3"

but register r28 was rewritten when kernel returns from exception
handler by value saved on stack.

This patch changed r3 saving to the correct address on the stack.
For example for r28:
by "swi r3, r1, 4 * 28"

When kernel returns from the exception handler, correct value is restored.

Signed-off-by: Michal Simek

microblaze: Do not use "la" pseudo instruction - use addik instead

2011-03-09T07:09:54+00:00

"la" pseudo instruction is only translation to "addik".
Use directly "addik" which is described in the MB reference guide.

Signed-off-by: Michal Simek

microblaze: Remove r0_ram pointer and PTO alignment

2011-03-09T07:09:54+00:00

r0_ram pool was used for saving/restoring register
content if hw exception happen. This poll was replaced by
pt_pool_space with PT_SIZE size.
Based on this change SAVE_STATE_ARG_SPACE was removed which
caused that PTO offset is zero that's why is also removed.

r0_ram space was used as scratchpad by v850. In early
Microblaze Linux developing phase was this part of code
blindly copied.

Signed-off-by: Michal Simek

microblaze: Do not use r0_ram space for hw exception debugging

2011-03-09T07:09:53+00:00

Remove hw exception counting space from r0_ram. Use special
exception_debug_table poll for exception statistic.

Signed-off-by: Michal Simek

microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1

2011-01-28T13:05:00+00:00

Unaligned code use shift for finding register operand.
There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1
by
	ori rD, r0, (1 << imm);	\
	idivu rD, rD, rA

but if rD is equal rA then ori instruction rewrite value which
should be devide.

The patch remove this macro which use idivu instruction because
idivu takes 32/34 cycles. The highest shifting is 20 which takes
20 cycles.

Signed-off-by: Michal Simek

microblaze: Fix unaligned exception for little endian platform

2011-01-03T09:08:29+00:00

Half word unaligned accesses need to be fixed.

Signed-off-by: Michal Simek

microblaze: Add stack unwinder

2010-08-04T08:22:35+00:00

Implement intelligent backtracing by searching for stack frame creation,
and emitting only return addresses. Use print_hex_dump() to display the
entire binary kernel stack.

Limitation: MMU kernels are not currently able to trace beyond a system trap
(interrupt, syscall, etc.). It is the intent of this patch to provide
infrastructure that can be extended to add this capability later.

Changes from V1:
* Removed checks in find_frame_creation() that prevented location of the frame
  creation instruction in heavily optimized code
* Various formatting/commenting/file location tweaks per review comments
* Dropped Kconfig option to enable STACKTRACE as something logically separate

Signed-off-by: Steven J. Magnani

microblaze: Use instruction with delay slot

2010-04-01T06:38:23+00:00

Sync labels.

Signed-off-by: Michal Simek

microblaze: Remove additional resr and rear loading

2010-04-01T06:38:23+00:00

RESR and REAR uses the same regs in whole file.

Signed-off-by: Michal Simek

microblaze: Change register usage for ESR and EAR

2010-04-01T06:38:23+00:00

This change synchronize register usage in code.
ESR = R4
EAR = R3

Signed-off-by: Michal Simek