linux-toradex.git/arch/microblaze, branch v2.6.38.2

microblaze: Fix /dev/zero corruption from __clear_user()

2011-03-23T20:03:39+00:00

commit 6f3946b421395ff853bc0bcdab9c26b50ebbba8f upstream.

A userland read of more than PAGE_SIZE bytes from /dev/zero results in
(a) not all of the bytes returned being zero, and
(b) memory corruption due to zeroing of bytes beyond the user buffer.

This is caused by improper constraints on the assembly __clear_user function.
The constrints don't indicate to the compiler that the pointer argument is
modified. Since the function is inline, this results in double-incrementing
of the pointer when __clear_user() is invoked through a multi-page read() of
/dev/zero.

Signed-off-by: Steven J. Magnani 
Acked-by: Michal Simek 
Signed-off-by: Greg Kroah-Hartman

microblaze: Fix msr instruction detection

2011-02-07T18:13:01+00:00

Fix msr instructions detection. The current code
just use msrclr for loading msr content and compare
it with proper MSR content. If msrclr is not implemented
r8 contains pc address.
Previous code wanted to use MSR carry bit but if msrclr
wasn't implemented carry wasn't cleared.

Signed-off-by: Michal Simek

microblaze: Fix pte_update function

2011-02-07T18:12:30+00:00

Do not disable irq in asm but use irq macros.
Systems with MSR=0 couldn't use pte_update function
because msrclr was hardcoded.

Signed-off-by: Michal Simek

microblaze: Fix asm compilation warning

2011-02-07T18:12:17+00:00

Microblaze ASM doesn't support hex values for mfs instructions.

/tmp/ccwiXVmt.s: Assembler messages:
/tmp/ccwiXVmt.s:19: Warning: ignoring operands: x00

Signed-off-by: Michal Simek

microblaze: Fix IRQ flag handling for MSR=0

2011-02-07T18:12:04+00:00

Patch: Fix IRQ flag handling naming
(sha1: f9ee29270c11dba7d0fe0b83ce47a4d8e8d2101)
introduced problem on system with MSR=0.

Signed-off-by: Michal Simek

microblaze: Fix ASM optimized code for LE

2011-01-28T13:05:13+00:00

Microblaze little-endian doesn't support ASM optimized library
functions(memcpy/memmove). Kconfig doens't contain
any information about endian that's why it is necessary to
check it in the source code.
The code is used with barrel shifter is used.

Signed-off-by: Michal Simek

microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1

2011-01-28T13:05:00+00:00

Unaligned code use shift for finding register operand.
There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1
by
	ori rD, r0, (1 << imm);	\
	idivu rD, rD, rA

but if rD is equal rA then ori instruction rewrite value which
should be devide.

The patch remove this macro which use idivu instruction because
idivu takes 32/34 cycles. The highest shifting is 20 which takes
20 cycles.

Signed-off-by: Michal Simek

microblaze: Fix DTB passing from bootloader

2011-01-28T13:04:36+00:00

Little endian system needs to check OF_DT_HEADER
but it is swapped because it is in big-endian.
Microblaze LE provides lwr instruction which loads
magic number in BIG endian format which can be compared.

There is used the fact that if you write 0x1 as word
and load it as byte then you get for big-endian zero
and 1 for little-endian.

Signed-off-by: Michal Simek

microblaze: Use generic irq Kconfig

2011-01-21T10:55:32+00:00

No functional change.

Signed-off-by: Thomas Gleixner 
Acked-by: Michal Simek

genirq: Remove __do_IRQ

2011-01-21T10:55:31+00:00

All architectures are finally converted. Remove the cruft.

Signed-off-by: Thomas Gleixner 
Cc: Richard Henderson 
Cc: Mike Frysinger 
Cc: David Howells 
Cc: Tony Luck 
Cc: Greg Ungerer 
Cc: Michal Simek 
Acked-by: David Howells 
Cc: Kyle McMartin 
Acked-by: Benjamin Herrenschmidt 
Cc: Chen Liqin 
Cc: "David S. Miller" 
Cc: Chris Metcalf 
Cc: Jeff Dike