linux-toradex.git/arch/mips/Kconfig, branch v4.3-rc2

kexec: split kexec_load syscall from kexec core code

2015-09-10T20:29:01+00:00

There are two kexec load syscalls, kexec_load another and kexec_file_load.
 kexec_file_load has been splited as kernel/kexec_file.c.  In this patch I
split kexec_load syscall code to kernel/kexec.c.

And add a new kconfig option KEXEC_CORE, so we can disable kexec_load and
use kexec_file_load only, or vice verse.

The original requirement is from Ted Ts'o, he want kexec kernel signature
being checked with CONFIG_KEXEC_VERIFY_SIG enabled.  But kexec-tools use
kexec_load syscall can bypass the checking.

Vivek Goyal proposed to create a common kconfig option so user can compile
in only one syscall for loading kexec kernel.  KEXEC/KEXEC_FILE selects
KEXEC_CORE so that old config files still work.

Because there's general code need CONFIG_KEXEC_CORE, so I updated all the
architecture Kconfig with a new option KEXEC_CORE, and let KEXEC selects
KEXEC_CORE in arch Kconfig.  Also updated general kernel code with to
kexec_load syscall.

[akpm@linux-foundation.org: coding-style fixes]
Signed-off-by: Dave Young 
Cc: Eric W. Biederman 
Cc: Vivek Goyal 
Cc: Petr Tesarik 
Cc: Theodore Ts'o 
Cc: Josh Boyer 
Cc: David Howells 
Cc: Geert Uytterhoeven 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2015-09-03T23:55:55+00:00

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 4.3 for MIPS.  Here's the summary:

  Three fixes that didn't make 4.2-stable:

   - a -Os build might compile the kernel using the MIPS16 instruction
     set but the R2 optimized inline functions in  are
     implemented using 32-bit wide instructions which is invalid.

   - a build error in pgtable-bits.h for a particular kernel
     configuration.

   - accessing registers of the CM GCR might have been compiled to use
     64 bit accesses but these registers are onl 32 bit wide.

  And also a few new bits:

   - move the ATH79 GPIO driver to drivers/gpio

   - the definition of IRQCHIP_DECLARE has moved to linux/irqchip.h,
     change ATH79 accordingly.

   - fix definition of pgprot_writecombine

   - add an implementation of dma_map_ops.mmap

   - fix alignment of quiet build output for vmlinuz link

   - BCM47xx: Use kmemdup rather than duplicating its implementation

   - Netlogic: Fix 0x0x prefixes of constants.

   - merge Bjorn Helgaas' series to remove most of the weak keywords
     from function declarations.

   - CP0 and CP1 registers are best considered treated as unsigned
     values to avoid large values from becoming negative values.

   - improve support for the MIPS GIC timer.

   - enable common clock framework for Malta and SEAD3.

   - a number of improvments and fixes to dump_tlb().

   - document the MIPS TLB dump functionality in Magic SysRq.

   - Cavium Octeon CN68XX improvments.

   - NetLogic improvments.

   - irq: Use access helper irq_data_get_affinity_mask.

   - handle MSA unaligned accesses.

   - a number of R6-related math-emu fixes.

   - support for I6400.

   - improvments to MSA support.

   - add uprobes support.

   - move from deprecated __initcall to arch_initcall.

   - remove finish_arch_switch().

   - IRQ cleanups by Thomas Gleixner.

   - migrate to new 'set-state' interface.

   - random small cleanups"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (148 commits)
  MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16.
  MIPS: Fix alignment of quiet build output for vmlinuz link
  MIPS: math-emu: Remove unused handle_dsemul function declaration
  MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 RINT FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction
  MIPS: math-emu: Add support for the CMP.condn.fmt R6 instruction
  MIPS: inst.h: Add new MIPS R6 FPU opcodes
  MIPS: Octeon: Fix management port MII address on Kontron S1901
  MIPS: BCM47xx: Use kmemdup rather than duplicating its implementation
  STAGING: Octeon: Use common helpers for determining interface and port
  MIPS: Octeon: Support interfaces 4 and 5
  MIPS: Octeon: Set up 1:1 mapping between CN68XX PKO queues and ports
  MIPS: Octeon: Initialize CN68XX PKO
  STAGING: Octeon: Support CN68XX style WQE
  ...

MIPS: pistachio: Allow to enable the external timer based clocksource

2015-09-03T10:08:07+00:00

This commit introduces a new config, so the user can choose to enable
the General Purpose Timer based clocksource. This option is required
to have CPUFreq support.

Signed-off-by: Ezequiel Garcia 
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Daniel Lezcano 
Cc: devicetree@vger.kernel.org
Cc: Thomas Gleixner 
Cc: Andrew Bresticker 
Cc: James Hartley 
Cc: Govindraj Raja 
Cc: Damien Horsley 
Cc: James Hogan 
Cc: Ezequiel Garcia 
Cc: Ezequiel Garcia 
Patchwork: http://patchwork.linux-mips.org/patch/10887/
Signed-off-by: Ralf Baechle

MIPS: Kconfig: Enable common clock framework for Malta and SEAD3

2015-09-03T10:08:06+00:00

Now that we're ready to enable COMMON_CLK for GIC platforms do so for
Malta and SEAD3.  The only other user of the GIC Pistachio does already
do so.

[ralf@linux-mips.org: Rewrite the commit message because applied in the
right order there is no breakage thus no fix required.]

Signed-off-by: Guenter Roeck 
Cc: Ezequiel Garcia 
Cc: Daniel Lezcano 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11038/
Signed-off-by: Ralf Baechle

MIPS: Add uprobes support.

2015-09-03T10:08:05+00:00

Signed-off-by: Ralf Baechle

MIPS: Netlogic: set ARCH_REQUIRE_GPIOLIB for XLP platform

2015-09-03T10:08:03+00:00

This is needed to enable GPIO framework support for Netlogic XLP platform.

Signed-off-by: Kamlakant Patel 
Signed-off-by: Jayachandran C 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10818/
Signed-off-by: Ralf Baechle

MIPS: Remove all the uses of custom gpio.h

2015-09-03T10:08:02+00:00

Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS
machines, and each machine type provides its own gpio.h. However
only a handful really implement the GPIO API, most just forward
everythings to gpiolib.

The Alchemy machine is notable as it provides a system to allow
implementing the GPIO API at the board level. But it is not used by
any board currently supported, so it can also be removed.

For most machine types we can just remove the custom gpio.h, as well
as the custom wrappers if some exists. Some of the code found in
the wrappers must be moved to the respective GPIO driver.

A few more fixes are need in some drivers as they rely on linux/gpio.h
to provides some machine specific definitions, or used asm/gpio.h
instead of linux/gpio.h for the gpio API.

Signed-off-by: Alban Bedel 
Reviewed-by: Linus Walleij 
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens 
Cc: Rafał Miłecki 
Cc: Bartlomiej Zolnierkiewicz 
Cc: Tejun Heo 
Cc: Alexandre Courbot 
Cc: Dmitry Torokhov 
Cc: Florian Fainelli 
Cc: Manuel Lauss 
Cc: Joe Perches 
Cc: Daniel Walter 
Cc: Sergey Ryazanov 
Cc: Huacai Chen 
Cc: James Hartley 
Cc: Andrew Bresticker 
Cc: Paul Burton 
Cc: Jiri Kosina 
Cc: Bjorn Helgaas 
Cc: Wolfram Sang 
Cc: Randy Dunlap 
Cc: Varka Bhadram 
Cc: Masanari Iida 
Cc: Tomi Valkeinen 
Cc: Michael Buesch 
Cc: abdoulaye berthe 
Cc: linux-kernel@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: netdev@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10828/
Signed-off-by: Ralf Baechle

MIPS: Select CONFIG_ARCH_USE_CMPXCHG_LOCKREF for MIPS64

2015-09-03T10:08:01+00:00

On MIPS64 we have spinlocks that are 32b in size and an efficient
cmpxchg64 implementation, so we qualify to make use of cmpxchg backed
lockrefs. Select the ARCH_USE_CMPXCHG_LOCKREF Kconfig symbol and provide
a trivial implementation of arch_spin_value_unlocked to satisfy the
lockref code.

Using Linus' simple testcase from
http://article.gmane.org/gmane.linux.file-systems/77466 on a dual core
system with an in-development MIPS64 CPU running on FPGA I see around an
8% gain:

Pre-patch:
    Total loops: 252698
    Total loops: 251482
    Total loops: 250806
    Total loops: 252885
    Total loops: 251666

Post-patch:
    Total loops: 273728
    Total loops: 269932
    Total loops: 269341
    Total loops: 275004
    Total loops: 270208

[ralf@linux-mips.org: Fixed conflict.]

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill 
Cc: linux-kernel@vger.kernel.org
Cc: Maciej W. Rozycki 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10810/
Signed-off-by: Ralf Baechle

MIPS: Drop EXPERIMENTAL tag from O32+FP64 & MSA

2015-09-03T10:08:00+00:00

CONFIG_MIPS_O32_FP64_SUPPORT and CONFIG_CPU_HAS_MSA are in pretty good
shape these days, and in much wider use than they once were. Stop
referring to them as EXPERIMENTAL.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10801/
Signed-off-by: Ralf Baechle

MIPS: Kconfig: Separate 32BIT and 64BIT config block by blank line.

2015-09-03T10:07:50+00:00

Signed-off-by: Ralf Baechle