linux-toradex.git/arch/mips/ar7, branch v3.2.18 Linux kernel for Apalis and Colibri modules MIPS: Mark cascade and low level interrupts IRQF_NO_THREAD 2011-09-21T15:52:15+00:00 Wu Zhangjin wuzhangjin@gmail.com 2011-07-23T12:41:24+00:00 5a4a4ad851dd8db2d888fb86c8bd946b2ae79f60 Mark interrupts with no_action handler, cascade interrupts, low level interrupts (bus error, halt ..) with IRQF_NO_THREAD to exclude them from forced threading. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Mark interrupts with no_action handler, cascade interrupts, low level
interrupts (bus error, halt ..) with IRQF_NO_THREAD to exclude them
from forced threading.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: AR7: Replace __attribute__((__packed__)) with __packed 2011-07-25T16:23:20+00:00 Florian Fainelli florian@openwrt.org 2011-06-12T18:57:19+00:00 c4a50541611d097c92f9e599f53d19d438074b12 Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2491/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org 
Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2491/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
MIPS: AR7: Remove 'space before tabs' in platform.c 2011-07-25T16:22:49+00:00 Florian Fainelli florian@openwrt.org 2011-06-12T18:57:18+00:00 11454100f41f43f128da02c0235ac85636a2cf70 Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2490/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2490/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: AR7: Fix trailing semicolon bug in clock.c 2011-07-20T22:12:12+00:00 Florian Fainelli florian@openwrt.org 2011-06-12T18:57:17+00:00 de8839728742a1745370b643f3ac771126dff12f Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2489/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2489/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: AR7: Fix GPIO register size for Titan variant. 2011-05-18T13:18:27+00:00 Florian Fainelli florian@openwrt.org 2011-05-13T15:41:21+00:00 3e9957b4866f3767f19bf0e543b322ad7906c564 The 'size' variable contains the correct register size for both AR7 and Titan, but we never used it to ioremap the correct register size. This problem only shows up on Titan. [ralf@linux-mips.org: Fixed the fix. The original patch as in patchwork recognizes the problem correctly then fails to fix it ...] Reported-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/2380/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
The 'size' variable contains the correct register size for both AR7
and Titan, but we never used it to ioremap the correct register size.
This problem only shows up on Titan.

[ralf@linux-mips.org: Fixed the fix.  The original patch as in patchwork
recognizes the problem correctly then fails to fix it ...]

Reported-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/2380/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Convert the irq functions to the new names 2011-03-29T12:48:07+00:00 Thomas Gleixner tglx@linutronix.de 2011-03-27T13:19:28+00:00 e4ec7989b4e55d9275ebac66230b7dac6dcb1fae Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> 
Scripted with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
MIPS: AR7: Convert to new irq_chip functions 2011-03-25T17:45:15+00:00 Thomas Gleixner tglx@linutronix.de 2011-03-23T21:08:46+00:00 41d735e8705c5a2cffe64bc56624a4bb0519c1da Signed-off-by: Thomas Gleixner <tglx@linutronix.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2174/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2174/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: AR7: Fix loops per jiffies on TNETD7200 devices 2010-12-16T18:10:56+00:00 Florian Fainelli florian@openwrt.org 2010-10-31T22:49:58+00:00 0bc6791707694c77b3543de39f77972a65de917a TNETD7200 run their CPU clock faster than the default CPU clock we assume. In order to have the correct loops per jiffies settings, initialize clocks right before setting mips_hpt_frequency. As a side effect, we can no longer use msleep in clocks.c which requires other parts of the kernel to be initialized, so replace these with mdelay. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
TNETD7200 run their CPU clock faster than the default CPU clock we assume.
In order to have the correct loops per jiffies settings, initialize clocks right
before setting mips_hpt_frequency. As a side effect, we can no longer use
msleep in clocks.c which requires other parts of the kernel to be initialized,
so replace these with mdelay.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1749/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant 2010-10-29T18:08:46+00:00 Florian Fainelli florian@openwrt.org 2010-08-29T15:08:44+00:00 238dd317f74250983aefbde6dc0a1f345a717993 Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost completely identical to AR7 except on a few points: - a second bank of gpios is available - vlynq0 on titan is vlynq1 on ar7 - different PHY addresses for cpmac0 This SoC can be found on commercial products like the Linksys WRTP54G Original patch by Xin with improvments by Florian. Signed-off-by: Xin Zhen <xlonestar2000@aim.com> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1563/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- 
Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost
completely identical to AR7 except on a few points:
- a second bank of gpios is available
- vlynq0 on titan is vlynq1 on ar7
- different PHY addresses for cpmac0

This SoC can be found on commercial products like the Linksys WRTP54G

Original patch by Xin with improvments by Florian.

Signed-off-by: Xin Zhen <xlonestar2000@aim.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1563/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
MIPS: AR7: Initialize GPIO earlier 2010-10-29T18:08:46+00:00 Florian Fainelli florian@openwrt.org 2010-08-29T15:08:41+00:00 3bc6968adc7b1926f4582a33a33ad42d9b302ce0 In order to detect the Titan variant, we must initialize GPIOs earlier since detection relies on some GPIO values to be set. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1562/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- 
In order to detect the Titan variant, we must initialize GPIOs earlier since
detection relies on some GPIO values to be set.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1562/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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