linux-toradex.git/arch/mips/bcm63xx/cpu.c, branch v3.9.2

MIPS: BCM63XX: Add basic BCM6328 support

2012-07-24T14:33:12+00:00

This includes CPU speed, memory size detection and working UART, but
lacking the appropriate drivers, no support for attached flash.

Signed-off-by: Jonas Gorski 
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon 
Cc: Florian Fainelli 
Cc: Kevin Cernekee 
Patchwork: https://patchwork.linux-mips.org/patch/3951/
Reviewed-by: Florian Fainelli 
Signed-off-by: Ralf Baechle

MIPS: BCM63XX: Use the Chip ID register for identifying the SoC

2012-07-24T14:33:12+00:00

Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the
revision bits. But since they all have the Chip ID register at the same
location, we can use that to identify the SoC we are running on.

Signed-off-by: Jonas Gorski 
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon 
Cc: Florian Fainelli 
Cc: Kevin Cernekee 
Patchwork: https://patchwork.linux-mips.org/patch/3955/
Reviewed-by: Florian Fainelli 
Signed-off-by: Ralf Baechle

MIPS: BCM63xx: Fix SDRAM size computation for BCM6345

2011-12-07T22:03:04+00:00

Instead of hardcoding the amount of available RAM, read the number of
effective multiples of 8MB from SDRAM_MBASE_REG.

Signed-off-by: Florian Fainelli 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3008/
Signed-off-by: Ralf Baechle

MIPS: BCM63XX: Add support for bcm6368 CPU.

2011-12-07T22:03:04+00:00

Signed-off-by: Maxime Bizon 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2892/
Signed-off-by: Ralf Baechle

MIPS: BCM63XX: Cleanup cpu registers.

2011-12-07T22:03:03+00:00

Use preprocessor when possible to avoid duplicated and error-prone
code.

Signed-off-by: Maxime Bizon 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2897/
Signed-off-by: Ralf Baechle

MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code

2010-10-29T18:08:50+00:00

BMIPS processor cores are used in 50+ different chipsets spread across
5+ product lines.  In many cases the chipsets do not share the same
peripheral register layouts, the same register blocks, the same
interrupt controllers, the same memory maps, or much of anything else.

But, across radically different SoCs that share nothing more than the
same BMIPS CPU, a few things are still mostly constant:

SMP operations
Access to performance counters
DMA cache coherency quirks
Cache and memory bus configuration

So, it makes sense to treat each BMIPS processor type as a generic
"building block," rather than tying it to a specific SoC.  This makes it
easier to support a large number of BMIPS-based chipsets without
unnecessary duplication of code, and provides the infrastructure needed
to support BMIPS-proprietary features.

Signed-off-by: Kevin Cernekee 
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Florian Fainelli 
Patchwork: https://patchwork.linux-mips.org/patch/1706/
Signed-off-by: Ralf Baechle

MIPS: BCM63xx: Add support for second uart.

2010-04-12T16:26:18+00:00

The BCm63xx SOC has two uarts.  Some boards use the second one for
bluetooth.  This patch changes platform device registration code to
handle this.  Changes to the UART driver were already merged in
6a2c7eabfd09ca7986bf96b8958a87ca041a19d8.

Signed-off-by: Maxime Bizon 
To: linux-mips@linux-mips.org
Cc: Maxime Bizon 
Patchwork: http://patchwork.linux-mips.org/patch/900/
Signed-off-by: Ralf Baechle

MIPS: bcm63xx: Set the correct BCM3302 CPU name

2009-11-02T11:00:07+00:00

For consistency with other BCM63xx SoC set the CPU name to "Broadcom
BCM6338" when actually running on that system.

Signed-off-by: Florian Fainelli 
Signed-off-by: Ralf Baechle

MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.

2009-09-17T18:07:52+00:00

Signed-off-by: Maxime Bizon 
Signed-off-by: Florian Fainelli 
Signed-off-by: Ralf Baechle