linux-toradex.git/arch/mips/boot/dts/mscc, branch v5.18

MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports

2021-08-21T08:38:48+00:00

The ocelot driver was converted to phylink, and that expects a valid
phy_interface_t. Without a phy-mode, of_get_phy_mode returns
PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that.

The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as
PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we
should fix the device trees and specify the phy-mode too.

Signed-off-by: Vladimir Oltean 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: ocelot: disable all switch ports by default

2021-08-21T08:38:29+00:00

The ocelot switch driver used to ignore ports which do not have a
phy-handle property and not probe those, but this is not quite ok since
it is valid to not have a phy-handle property if there is a fixed-link.

It seems that checking for a phy-handle was a proxy for the proper check
which is for the status, but that doesn't make a lot of sense, since the
ocelot driver already iterates using for_each_available_child_of_node
which skips the disabled ports, so I have no idea.

Anyway, a widespread pattern in device trees is for a SoC dtsi to
disable by default all hardware, and let board dts files enable what is
used. So let's do that and enable only the ports with a phy-handle in
the pcb120 and pcb123 device tree files.

Signed-off-by: Vladimir Oltean 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add serval support

2020-11-12T22:35:15+00:00

Add a device trees and FIT image support for the Microsemi Serval SoC
which belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen .

Signed-off-by: Gregory CLEMENT 
Acked-by: Alexandre Belloni 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add jaguar2 support

2020-11-12T22:34:25+00:00

Add a device trees and FIT image support for the Microsemi Jaguar2 SoC
which belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen .

Signed-off-by: Gregory CLEMENT 
Acked-by: Alexandre Belloni 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add luton PC0B91 device tree

2020-11-12T22:33:42+00:00

Add a device tree for the Microsemi Luton PCB091 evaluation board.

It is based on the work of Lars Povlsen .

Signed-off-by: Gregory CLEMENT 
Acked-by: Alexandre Belloni 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add luton dtsi

2020-11-12T22:32:39+00:00

Add a device tree include file for the Microsemi Luton SoC which
belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen .

Signed-off-by: Gregory CLEMENT 
Acked-by: Alexandre Belloni 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Prepare configuration to handle more SoCs

2020-11-12T22:31:47+00:00

Ocelot belongs to a family of SoC named the VCore III. In order to add
these new Soc, use the new symbol SOC_VCOREIII instead of a one
dedicated to Ocelot.

In order to avoid regression on driver building, the MSCC_OCELOT
configuration symbol is kept until the driver will be converted.

Signed-off-by: Gregory CLEMENT 
Acked-by: Alexandre Belloni 
Signed-off-by: Thomas Bogendoerfer

net: mscc: ocelot: add definitions for VCAP ES0 keys, actions and target

2020-09-30T01:26:12+00:00

As a preparation step for the offloading to ES0, let's create the
infrastructure for talking with this hardware block.

Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

net: mscc: ocelot: add definitions for VCAP IS1 keys, actions and target

2020-09-30T01:26:12+00:00

As a preparation step for the offloading to IS1, let's create the
infrastructure for talking with this hardware block.

Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

MIPS: dts: ocelot: describe the load/save GPIO

2020-06-24T21:33:16+00:00

This patch adds a description of the load/save GPIN pin, used in the
VSC8584 PHY for timestamping operations. The related pinctrl description
is also added.

Signed-off-by: Quentin Schulz 
Signed-off-by: Antoine Tenart 
Signed-off-by: David S. Miller