linux-toradex.git/arch/mips/dec/setup.c, branch v3.19

MIPS: DEC: Remove the Halt button interrupt on R4k systems

2014-05-30T19:01:08+00:00

On R4k DECstations the Halt button is wired to the NMI processor input
rather than an ordinary interrupt input such as on R3k DECstations.  This
is possible with a different design of the CPU daughtercard that routes
the Halt button line from the baseboard connector.  Additionally the
interrupt input has been reused for a different purpose on the KN04 and
KN05 R4k CPU daughtercards so it is better kept masked.

Signed-off-by: Maciej W. Rozycki 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6705/
Signed-off-by: Ralf Baechle

DEC: Whitespace cleanup

2013-10-29T20:24:44+00:00

Commit 7034228792cc561e79ff8600f02884bd4c80e287 [MIPS: Whitespace
cleanup.] did a lot of good and a little damage.  Revert the damage.

Signed-off-by: Maciej W. Rozycki 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5875/
Signed-off-by: Ralf Baechle

MIPS: Whitespace cleanup.

2013-02-01T09:00:22+00:00

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle

MIPS: irq: Remove IRQF_DISABLED

2011-12-07T22:03:45+00:00

Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled],
We run all interrupt handlers with interrupts disabled and we even check
and yell when an interrupt handler returns with interrupts enabled (see
commit [b738a50a: genirq: Warn when handler enables interrupts]).

So now this flag is a NOOP and can be removed.

[ralf@linux-mips.org: Fixed up conflicts in
arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and
arch/mips/kernel/perf_event.c.]

Signed-off-by: Yong Zhang 
To: linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de
linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2835/
Signed-off-by: Ralf Baechle

MIPS: Mark cascade and low level interrupts IRQF_NO_THREAD

2011-09-21T15:52:15+00:00

Mark interrupts with no_action handler, cascade interrupts, low level
interrupts (bus error, halt ..) with IRQF_NO_THREAD to exclude them
from forced threading.

Signed-off-by: Wu Zhangjin 
Signed-off-by: Thomas Gleixner 
Cc: linux-mips@linux-mips.org
Cc: Wu Zhangjin 
Signed-off-by: Ralf Baechle

MIPS: Add missing #inclusions of

2010-10-07T13:08:54+00:00

Add missing #inclusions of  to a whole bunch of files that should
really include it.  Note that this can replace #inclusions of .

This is required for the patch to sort out irqflags handling function naming to
compile on MIPS.

The problem is that these files require access to things like setup_irq() -
which isn't available by #including 

Signed-off-by: David Howells 
Acked-by: Ralf Baechle

[MIPS] Deforest the function pointer jungle in the time code.

2007-10-11T22:46:08+00:00

Hard to follow who is pointing what to where and why so it's simply getting
in the way of the time code renovation.

Signed-off-by: Ralf Baechle

[MIPS] DEC: Initialise ioasic_ssr_lock

2007-09-19T18:33:14+00:00

Fix the definition of the ioasic_ssr_lock spinlock to include a proper 
initialisation.

Signed-off-by: Maciej W. Rozycki 
Signed-off-by: Ralf Baechle

[TC] TURBOchannel support for the DECstation

2007-02-09T16:23:16+00:00

This is the platform-specific part of TURBOchannel bus support for the
DECstation.  It implements determining whether the bus is actually there,
getting bus parameters, IRQ assignments for devices and protected accesses
to possibly unoccupied slots that may trigger bus error exceptions.

Signed-off-by: Maciej W. Rozycki 
Signed-off-by: Andrew Morton 
Signed-off-by: Ralf Baechle

[MIPS] Define MIPS_CPU_IRQ_BASE in generic header

2007-02-06T16:53:08+00:00

The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto 
Signed-off-by: Ralf Baechle