linux-toradex.git/arch/mips/include/asm/mipsregs.h, branch v5.18

MIPS: remove asm/war.h

2022-02-22T08:35:49+00:00

The major part for workaround handling has already moved to config
options. This change replaces the remaining defines by already
available config options and gets rid of war.h

Signed-off-by: Thomas Bogendoerfer

MIPS: Avoid macro redefinitions

2021-09-23T09:23:35+00:00

To be able to compile the kernel with LTO, the assembler macros cannot
be declared in the global scope, or the compiler will complain about
redefined macros.

Update the code so that macros are defined then undefined when they are
used.

Note that virt support was added in 2.24 and xpa in 2.25. So we still
need the TOOLCHAIN defines for them.

Signed-off-by: Paul Cercueil 
Reviewed-by: Nick Desaulniers 
Signed-off-by: Thomas Bogendoerfer

MIPS: set mips32r5 for virt extensions

2021-06-29T08:23:57+00:00

Clang's integrated assembler only accepts these instructions when the
cpu is set to mips32r5. With this change, we can assemble
malta_defconfig with Clang via `make LLVM_IAS=1`.

Link: https://github.com/ClangBuiltLinux/linux/issues/763
Reported-by: Dmitry Golovin 
Signed-off-by: Nick Desaulniers 
Signed-off-by: Thomas Bogendoerfer

MIPS: Make check condition for SDBBP consistent with EJTAG spec

2021-02-11T10:04:31+00:00

According to MIPS EJTAG Specification [1], a Debug Breakpoint
exception occurs when an SDBBP instruction is executed, the
CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception
occurred.

When I read the original code, it looks a little confusing
at first glance, just check bit DBp for SDBBP to make the
code more readable, it will be much easier to understand.

[1] http://www.t-es-t.hu/download/mips/md00047f.pdf

Signed-off-by: Tiezhu Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: Loongson-3: Enable COP2 usage in kernel

2020-09-21T20:15:03+00:00

Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel
mode by default. However, gslq/gssq (16-bytes load/store instructions)
overrides the instruction format of lwc2/swc2. If we wan't to use gslq/
gssq for optimization in kernel, we should enable COP2 usage in kernel.

Please pay attention that in this patch we only enable COP2 in kernel,
which means it will lose ST0_CU2 when a process go to user space (try
to use COP2 in user space will trigger an exception and then grab COP2,
which is similar to FPU). And as a result, we need to modify the context
switching code because the new scheduled process doesn't contain ST0_CU2
in its THERAD_STATUS probably.

For zboot, we disable gslq/gssq be generated by toolchain.

Signed-off-by: Huacai Chen 
Signed-off-by: Thomas Bogendoerfer

MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option

2020-09-07T20:24:40+00:00

Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer

MIPS: Remove PNX833x alias NXP_STB22x

2020-08-24T15:29:28+00:00

Remove another unused MIPS platform.

Signed-off-by: Thomas Bogendoerfer

MIPS: handle Loongson-specific GSExc exception

2020-07-31T15:52:47+00:00

Newer Loongson cores (Loongson-3A R2 and newer) use the
implementation-dependent ExcCode 16 to signal Loongson-specific
exceptions. The extended cause is put in the non-standard CP0.Diag1
register which is CP0 Register 22 Select 1, called GSCause in Loongson
manuals. Inside is an exception code bitfield called GSExcCode, only
codes 0 to 6 inclusive are documented (so far, in the Loongson 3A3000
User Manual, Volume 2).

During experiments, it was found that some undocumented unprivileged
instructions can trigger the also-undocumented GSExcCode 8 on Loongson
3A4000. Processor state is not corrupted, but we cannot continue without
further knowledge, and Loongson is not providing that information as of
this writing. So we send SIGILL on seeing this exception code to thwart
easy local DoS attacks.

Other exception codes are made fatal, partly because of insufficient
knowledge, also partly because they are not as easily reproduced. None
of them are encountered in the wild with upstream kernels and userspace
so far.

Some older cores (Loongson-3A1000 and Loongson-3B1500) have ExcCode 16
too, but the semantic is equivalent to GSExcCode 0. Because the
respective manuals did not mention the CP0.Diag1 register or its read
behavior, these cores are not covered in this patch, as MFC0 from
non-existent CP0 registers is UNDEFINED according to the MIPS
architecture spec.

Reviewed-by: Huacai Chen 
Signed-off-by: WANG Xuerui 
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: Tiezhu Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: add definitions for Loongson-specific CP0.Diag1 register

2020-07-31T15:52:29+00:00

This 32-bit CP0 register is named GSCause in Loongson manuals. It carries
Loongson extended exception information. We name it Diag1 because we
fear the "GSCause" name might get changed in the future.

Reviewed-by: Huacai Chen 
Signed-off-by: WANG Xuerui 
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: Tiezhu Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: Unify naming style of vendor CP0.Config6 bits

2020-07-08T09:15:53+00:00

Other vendor-defined registers use the vendor name as a prefix, not an
infix, so unify the naming style of CP0.Config6 bits.

Suggested-by: Maciej W. Rozycki" 
Signed-off-by: Huacai Chen 
Reviewed-by: Maciej W. Rozycki 
Signed-off-by: Thomas Bogendoerfer