linux-toradex.git/arch/mips/include/asm/mmu_context.h, branch v3.1.2

MIPS: Use C0_KScratch (if present) to hold PGD pointer.

2011-01-18T18:30:22+00:00

Decide at runtime to use either Context or KScratch to hold the PGD
pointer.

Signed-off-by: David Daney 
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1876/
Signed-off-by: Ralf Baechle

MIPS: Preliminary VDSO

2010-04-12T16:26:14+00:00

This is a preliminary patch to add a vdso to all user processes.  Still
missing are ELF headers and .eh_frame information.  But it is enough to
allow us to move signal trampolines off of the stack.  Note that emulation
of branch delay slots in the FPU emulator still requires the stack.

We allocate a single page (the vdso) and write all possible signal
trampolines into it.  The stack is moved down by one page and the vdso is
mapped into this space.

Signed-off-by: David Daney 
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/975/
Signed-off-by: Ralf Baechle

MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.

2009-12-17T01:57:01+00:00

Processors that support the mips64r2 ISA can in four instructions
convert a shifted PGD pointer stored in the upper bits of c0_context
into a usable pointer.  By doing this we save a memory load and
associated potential cache miss in the TLB exception handlers.

Since the upper bits of c0_context were holding the CPU number, we
move this to the upper bits of c0_xcontext which doesn't have enough
bits to hold the PGD pointer, but has plenty for the CPU number.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Avoid potential hazard on Context register

2009-11-02T11:00:07+00:00

set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.

Issue found and fixed for head.S by Chris Dearman .

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: Don't write ones to reserved entryhi bits.

2009-11-02T11:00:01+00:00

We've silently been relying on the hardware chopping off excess, reserved
ASID bits for no better reason that it saving an instruction.  Because we
already have:

#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)

in .

We can use a cleanup to avoid writing non-zero bits into the reserved
entryhi bits.  This avoid triggering some debugging assertion in the
Cavium simulator.

Signed-off-by: Ralf Baechle

cpumask: use mm_cpumask() wrapper: mips

2009-09-24T00:04:51+00:00

Makes code futureproof against the impending change to mm->cpu_vm_mask.

It's also a chance to use the new cpumask_ ops which take a pointer
(the older ones are deprecated, but there's no hurry for arch code).

Signed-off-by: Rusty Russell

MIPS: Build fix - include into all smp_processor_id() users.

2009-06-24T17:34:39+00:00

Some of the were relying into smp.h being dragged in by another header
which of course is fragile.   uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.

Signed-off-by: Ralf Baechle

MIPS: Move headfiles to new location below arch/mips/include

2008-10-11T15:18:52+00:00

Signed-off-by: Ralf Baechle