<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/mips/include/asm/module.h, branch v3.6.4</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>MIPS: Fix race condition in module relocation code.</title>
<updated>2012-08-17T08:57:28+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2012-08-08T14:59:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=861667dc82f561e65336ea67f73021b782b4ff74'/>
<id>861667dc82f561e65336ea67f73021b782b4ff74</id>
<content type='text'>
The relocation code was essentially taken from the 2.4 modutils which
perform relocation in userspace.  In 2.6 relocation of multiple modules
may be performed in parallel by the in-kernel loader so the global
variable mips_hi16_list won't fly anymore.  Fix race by moving it into
mod_arch_specific.

[ralf@linux-mips.org: folded in Tony's followup fix.  Thanks Tony!]

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Tony Wu &lt;tung7970@gmail.com&gt;
Cc:  linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4189/
</content>
<content type='xhtml'>
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<pre>
The relocation code was essentially taken from the 2.4 modutils which
perform relocation in userspace.  In 2.6 relocation of multiple modules
may be performed in parallel by the in-kernel loader so the global
variable mips_hi16_list won't fly anymore.  Fix race by moving it into
mod_arch_specific.

[ralf@linux-mips.org: folded in Tony's followup fix.  Thanks Tony!]

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Tony Wu &lt;tung7970@gmail.com&gt;
Cc:  linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4189/
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Add CPU support for Loongson1B</title>
<updated>2012-07-23T12:57:04+00:00</updated>
<author>
<name>Kelvin Cheung</name>
<email>keguang.zhang@gmail.com</email>
</author>
<published>2012-06-20T19:05:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2fa36399e63c911134f28b6878aada9b395c4209'/>
<id>2fa36399e63c911134f28b6878aada9b395c4209</id>
<content type='text'>
Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology
(ICT) and the Chinese Academy of Sciences (CAS), which implements the
MIPS32 release 2 instruction set.

[ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device
which also is why it identifies itself with the Legacy Vendor ID in the
PrID register.  When applying the patch I shoveled some code around to
keep things in alphabetical order and avoid forward declarations.]

Signed-off-by: Kelvin Cheung &lt;keguang.zhang@gmail.com&gt;
Cc: To: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung &lt;keguang.zhang@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/3976/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology
(ICT) and the Chinese Academy of Sciences (CAS), which implements the
MIPS32 release 2 instruction set.

[ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device
which also is why it identifies itself with the Legacy Vendor ID in the
PrID register.  When applying the patch I shoveled some code around to
keep things in alphabetical order and avoid forward declarations.]

Signed-off-by: Kelvin Cheung &lt;keguang.zhang@gmail.com&gt;
Cc: To: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung &lt;keguang.zhang@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/3976/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Delete bogus module.h usage in termios.h</title>
<updated>2012-05-15T15:48:51+00:00</updated>
<author>
<name>Paul Gortmaker</name>
<email>paul.gortmaker@windriver.com</email>
</author>
<published>2012-02-29T00:24:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4ca98d399e66899222f1d457731b7857e85e09f1'/>
<id>4ca98d399e66899222f1d457731b7857e85e09f1</id>
<content type='text'>
There is no need for this.  Removing it causes a small amount of fallout
(shown below) due to a few implicit header presence assumptions that are
easily fixed.

arch/mips/include/asm/termios.h:103: error: implicit declaration of function 'access_ok'
arch/mips/include/asm/module.h:17: error: expected specifier-qualifier-list before 'Elf64_Addr'

Signed-off-by: Paul Gortmaker &lt;paul.gortmaker@windriver.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3449/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is no need for this.  Removing it causes a small amount of fallout
(shown below) due to a few implicit header presence assumptions that are
easily fixed.

arch/mips/include/asm/termios.h:103: error: implicit declaration of function 'access_ok'
arch/mips/include/asm/module.h:17: error: expected specifier-qualifier-list before 'Elf64_Addr'

Signed-off-by: Paul Gortmaker &lt;paul.gortmaker@windriver.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3449/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branches 'next/ar7', 'next/ath79', 'next/bcm63xx', 'next/bmips', 'next/cavium', 'next/generic', 'next/kprobes', 'next/lantiq', 'next/perf' and 'next/raza' into mips-for-linux-next</title>
<updated>2012-01-11T14:42:31+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2012-01-11T14:42:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7bf6612e8a9d6a0b3b82e8e2611942be1258b307'/>
<id>7bf6612e8a9d6a0b3b82e8e2611942be1258b307</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Netlogic: XLP CPU support.</title>
<updated>2011-12-07T22:04:55+00:00</updated>
<author>
<name>Jayachandran C</name>
<email>jayachandranc@netlogicmicro.com</email>
</author>
<published>2011-11-16T00:21:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a3d4fb2d2a4c52b22cde90049a78e323cde187e5'/>
<id>a3d4fb2d2a4c52b22cde90049a78e323cde187e5</id>
<content type='text'>
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h

Signed-off-by: Jayachandran C &lt;jayachandranc@netlogicmicro.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2966/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h

Signed-off-by: Jayachandran C &lt;jayachandranc@netlogicmicro.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2966/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS</title>
<updated>2011-12-07T22:03:17+00:00</updated>
<author>
<name>Kevin Cernekee</name>
<email>cernekee@gmail.com</email>
</author>
<published>2011-11-16T01:25:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1c7c44519a12d79af1f599a8cc4997e1230025ed'/>
<id>1c7c44519a12d79af1f599a8cc4997e1230025ed</id>
<content type='text'>
Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel
images will compile and run.

Signed-off-by: Kevin Cernekee &lt;cernekee@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2955/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel
images will compile and run.

Signed-off-by: Kevin Cernekee &lt;cernekee@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2955/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Netlogic: Cache, TLB support and feature overrides for XLR</title>
<updated>2011-05-19T08:55:40+00:00</updated>
<author>
<name>Jayachandran C</name>
<email>jayachandranc@netlogicmicro.com</email>
</author>
<published>2011-05-06T20:06:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=efa0f81c11021c95b1e72c65868115b6fb4ecc6a'/>
<id>efa0f81c11021c95b1e72c65868115b6fb4ecc6a</id>
<content type='text'>
CPU_XLR case added to mm/tlbex.c
CPU_XLR case added to mm/c-r4k.c for PINDEX attribute
Feature overrides for XLR cpu.

Signed-off-by: Jayachandran C &lt;jayachandranc@netlogicmicro.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2333/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
CPU_XLR case added to mm/tlbex.c
CPU_XLR case added to mm/c-r4k.c for PINDEX attribute
Feature overrides for XLR cpu.

Signed-off-by: Jayachandran C &lt;jayachandranc@netlogicmicro.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2333/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Add Cavium OCTEON processor constants and CPU probe.</title>
<updated>2009-01-11T09:57:22+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2008-12-11T23:33:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0dd4781bca56871434507ed35d5bb8ef92077907'/>
<id>0dd4781bca56871434507ed35d5bb8ef92077907</id>
<content type='text'>
Add OCTEON constants to asm/cpu.h and asm/module.h.

Add probe function for Cavium OCTEON CPUs and hook it up.

Signed-off-by: Tomaso Paoletti &lt;tpaoletti@caviumnetworks.com&gt;
Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add OCTEON constants to asm/cpu.h and asm/module.h.

Add probe function for Cavium OCTEON CPUs and hook it up.

Signed-off-by: Tomaso Paoletti &lt;tpaoletti@caviumnetworks.com&gt;
Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processors</title>
<updated>2008-10-27T16:18:29+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2008-10-23T16:27:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=542c1020ac1cbc2f50934086ad893384a2cbd233'/>
<id>542c1020ac1cbc2f50934086ad893384a2cbd233</id>
<content type='text'>
We already have sufficient infrastructure to support VR5500 and VR5500A
series processors.  Here's a Makefile support to make it selectable by
ports, and enable it for NEC EMMA2RH Markeins board.

This patch also fixes a confused target help, and adds 1Gb PageMask bits
supported by VR5500 and its variants.

Signed-off-by: Shinya Kuribayashi &lt;shinya.kuribayashi@necel.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We already have sufficient infrastructure to support VR5500 and VR5500A
series processors.  Here's a Makefile support to make it selectable by
ports, and enable it for NEC EMMA2RH Markeins board.

This patch also fixes a confused target help, and adds 1Gb PageMask bits
supported by VR5500 and its variants.

Signed-off-by: Shinya Kuribayashi &lt;shinya.kuribayashi@necel.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Move headfiles to new location below arch/mips/include</title>
<updated>2008-10-11T15:18:52+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2008-09-16T17:48:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=384740dc49ea651ba350704d13ff6be9976e37fe'/>
<id>384740dc49ea651ba350704d13ff6be9976e37fe</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
