<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/mips/include/asm/octeon, branch v3.2.4-rt10</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Fix common misspellings</title>
<updated>2011-03-31T14:26:23+00:00</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@profusion.mobi</email>
</author>
<published>2011-03-31T01:57:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=25985edcedea6396277003854657b5f3cb31a628'/>
<id>25985edcedea6396277003854657b5f3cb31a628</id>
<content type='text'>
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@profusion.mobi&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@profusion.mobi&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Rewrite interrupt handling code.</title>
<updated>2011-03-29T12:48:06+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2011-03-25T19:38:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0c3263870f5f80cf7b6cb322bd8e708ce568d36b'/>
<id>0c3263870f5f80cf7b6cb322bd8e708ce568d36b</id>
<content type='text'>
This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.

The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.

[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
        __irq_set_affinity_lock ]

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
LKML-Reference: &lt;1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.

The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.

[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
        __irq_set_affinity_lock ]

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
LKML-Reference: &lt;1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.</title>
<updated>2010-10-29T18:08:43+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-10-08T21:47:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4169b86324fbefdf137a0bd69154d0e874f2bec2'/>
<id>4169b86324fbefdf137a0bd69154d0e874f2bec2</id>
<content type='text'>
The EHCI and OHCI blocks connection to the I/O bus is controlled by
these registers.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1674/
Acked-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;

 create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The EHCI and OHCI blocks connection to the I/O bus is controlled by
these registers.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1674/
Acked-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;

 create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Add octeon_get_io_clock_rate() for cn63xx</title>
<updated>2010-10-29T18:08:40+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-10-07T23:03:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e195aa3039c5c4eeb60c415a7a0f3006d5cdcd3b'/>
<id>e195aa3039c5c4eeb60c415a7a0f3006d5cdcd3b</id>
<content type='text'>
Starting with cn63xx Octeon I/O blocks are clocked at a different rate
than the CPU.  Add a new function octeon_get_io_clock_rate() that
yields the I/O clock rate.

Also rearrange octeon_get_clock_rate() to get the value from the saved
sysinfo structure.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1671/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Starting with cn63xx Octeon I/O blocks are clocked at a different rate
than the CPU.  Add a new function octeon_get_io_clock_rate() that
yields the I/O clock rate.

Also rearrange octeon_get_clock_rate() to get the value from the saved
sysinfo structure.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1671/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Update L2 Cache code for CN63XX</title>
<updated>2010-10-29T18:08:35+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-10-07T23:03:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b8db85b5b5c22236d168eb03a67c2641bf7fa651'/>
<id>b8db85b5b5c22236d168eb03a67c2641bf7fa651</id>
<content type='text'>
The CN63XX has a different L2 cache architecture.  Update the helper
functions to reflect this.

Some joining of split lines was also done to improve readability, as
well as reformatting of comments.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1663/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The CN63XX has a different L2 cache architecture.  Update the helper
functions to reflect this.

Some joining of split lines was also done to improve readability, as
well as reformatting of comments.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1663/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Add cn63XX to Octeon chip detection macros.</title>
<updated>2010-10-29T18:08:34+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-10-07T23:03:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a70b13a9f07ae0e21870ed3e9b6829f556579c5c'/>
<id>a70b13a9f07ae0e21870ed3e9b6829f556579c5c</id>
<content type='text'>
Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1661/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1661/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Update register definitions for CN63XX chips</title>
<updated>2010-10-29T18:08:33+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-10-07T23:03:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=aa32a955ae46d4117e880417c89a2efcc88579c2'/>
<id>aa32a955ae46d4117e880417c89a2efcc88579c2</id>
<content type='text'>
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Rewrite DMA mapping functions.</title>
<updated>2010-10-29T18:08:32+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-10-01T20:27:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b93b2abce497873be97d765b848e0a955d29f200'/>
<id>b93b2abce497873be97d765b848e0a955d29f200</id>
<content type='text'>
All Octeon chips can support more than 4GB of RAM.  Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.

Enable the swiotlb code to handle the cases where a device cannot directly
do DMA.  This is a complete rewrite of the Octeon DMA mapping code.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All Octeon chips can support more than 4GB of RAM.  Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.

Enable the swiotlb code to handle the cases where a device cannot directly
do DMA.  This is a complete rewrite of the Octeon DMA mapping code.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Allow more than 3.75GB of memory with PCIe</title>
<updated>2010-08-05T12:26:31+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-08-04T21:53:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2b5987abaf2dd6c3934e0376b7d9f64411cdcf03'/>
<id>2b5987abaf2dd6c3934e0376b7d9f64411cdcf03</id>
<content type='text'>
We reserve the 3.75GB - 4GB region of PCIe address space for device to
device transfers, making the corresponding physical memory under
direct mapping unavailable for DMA.

To allow for PCIe DMA to all physical memory we map this chunk of
physical memory with BAR1.  Because of the resulting discontinuity in
the mapping function, we remove a page of memory at each end of the
range so multi-page DMA buffers can never be allocated that span the
range.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1535/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We reserve the 3.75GB - 4GB region of PCIe address space for device to
device transfers, making the corresponding physical memory under
direct mapping unavailable for DMA.

To allow for PCIe DMA to all physical memory we map this chunk of
physical memory with BAR1.  Because of the resulting discontinuity in
the mapping function, we remove a page of memory at each end of the
range so multi-page DMA buffers can never be allocated that span the
range.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1535/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Octeon: Implement delays with cycle counter.</title>
<updated>2010-08-05T12:26:20+00:00</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2010-06-01T20:18:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=ca148125e6134de334b61822539d220794d8da18'/>
<id>ca148125e6134de334b61822539d220794d8da18</id>
<content type='text'>
Power throttling make deterministic delay loops impossible.
Re-implement delays using the cycle counter.  This also allows us to
get rid of the code that calculates loops per jiffy.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1317/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Power throttling make deterministic delay loops impossible.
Re-implement delays using the cycle counter.  This also allows us to
get rid of the code that calculates loops per jiffy.

Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1317/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
