linux-toradex.git/arch/mips/include/asm/stackframe.h, branch v3.10.2 Linux kernel for Apalis and Colibri modules MIPS: microMIPS: Add support for exception handling. 2013-05-09T15:55:18+00:00 Steven J. Hill Steven.Hill@imgtec.com 2013-03-25T17:15:55+00:00 2a0b24f56c2492b932f1aed617ae80fb23500d21 All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> 
All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
MIPS: Whitespace cleanup. 2013-02-01T09:00:22+00:00 Ralf Baechle ralf@linux-mips.org 2013-01-22T11:59:30+00:00 7034228792cc561e79ff8600f02884bd4c80e287 Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC 2011-09-21T15:54:02+00:00 David Daney david.daney@cavium.com 2011-08-30T13:45:20+00:00 d968275921f9fa7fbc602ac6618ffec6a062ee3c Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/2753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/2753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix common misspellings 2011-03-31T14:26:23+00:00 Lucas De Marchi lucas.demarchi@profusion.mobi 2011-03-31T01:57:33+00:00 25985edcedea6396277003854657b5f3cb31a628 Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi> 
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds. 2010-04-30T19:52:58+00:00 Wu Zhangjin wuzhangjin@gmail.com 2010-04-10T12:07:01+00:00 b197b6286650feb9c991826519065aac6f4399b1 Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1106/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Loongson-2F: Flush the branch target history in BTB and RAS 2010-04-12T16:26:15+00:00 Wu Zhangjin wuzhangjin@gmail.com 2010-03-13T04:34:15+00:00 f1df323924e2fde14cbcd51209a8cbfc33e0c232 As per chapter 15 "Errata: Issue of Out-of-order in loongson"[1] to work around the Loongson 2F erratum we need to do: "When switching from user mode to kernel mode, you should flush the branch target history such as BTB and RAS." [1] Chinese version: http://www.loongson.cn/uploadfile/file/200808211 [2] English version of chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Patchwork: http://patchwork.linux-mips.org/patch/1066/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
As per chapter 15 "Errata: Issue of Out-of-order in loongson"[1] to work
around the Loongson 2F erratum we need to do:

"When switching from user mode to kernel mode, you should flush the
branch target history such as BTB and RAS."

[1] Chinese version: http://www.loongson.cn/uploadfile/file/200808211
[2] English version of chapter 15:
    http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Patchwork: http://patchwork.linux-mips.org/patch/1066/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors. 2009-12-17T01:57:01+00:00 David Daney ddaney@caviumnetworks.com 2009-10-14T19:16:56+00:00 82622284dd2f8791f9759f3cef601520a8bc63b2 Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Processors that support the mips64r2 ISA can in four instructions
convert a shifted PGD pointer stored in the upper bits of c0_context
into a usable pointer.  By doing this we save a memory load and
associated potential cache miss in the TLB exception handlers.

Since the upper bits of c0_context were holding the CPU number, we
move this to the upper bits of c0_xcontext which doesn't have enough
bits to hold the PGD pointer, but has plenty for the CPU number.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Reorder operations in stackframe.h for better scheduling 2009-12-17T01:56:57+00:00 David Daney ddaney@caviumnetworks.com 2009-06-26T16:01:43+00:00 362e696428590f7d0a5d0971a2d04b0372a761b8 Reorder PT ops to avoid pipeline stalls. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Reorder PT ops to avoid pipeline stalls.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Cavium OCTEON multiplier state preservation. 2009-01-11T09:57:24+00:00 David Daney ddaney@caviumnetworks.com 2008-12-11T23:33:33+00:00 2a219b0eaa7bb9f1a7dae4e8ac5b1bf68adab289 For OCTEON, implement a save and restore of the multiplier state across context switches. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
For OCTEON, implement a save and restore of the multiplier state
across context switches.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Move headfiles to new location below arch/mips/include 2008-10-11T15:18:52+00:00 Ralf Baechle ralf@linux-mips.org 2008-09-16T17:48:51+00:00 384740dc49ea651ba350704d13ff6be9976e37fe Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>