linux-toradex.git/arch/mips/include/asm, branch v2.6.32.31

MIPS: Quit using undefined behavior of ADDU in 64-bit atomic operations.

2010-09-27T00:21:39+00:00

commit f2a68272d799bf4092443357142f63b74f7669a1 upstream.

For 64-bit, we must use DADDU and DSUBU.

Signed-off-by: David Daney 
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1483/
Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

compat: Make compat_alloc_user_space() incorporate the access_ok()

2010-09-20T20:17:57+00:00

commit c41d68a513c71e35a14f66d71782d27a79a81ea6 upstream.

compat_alloc_user_space() expects the caller to independently call
access_ok() to verify the returned area.  A missing call could
introduce problems on some architectures.

This patch incorporates the access_ok() check into
compat_alloc_user_space() and also adds a sanity check on the length.
The existing compat_alloc_user_space() implementations are renamed
arch_compat_alloc_user_space() and are used as part of the
implementation of the new global function.

This patch assumes NULL will cause __get_user()/__put_user() to either
fail or access userspace on all architectures.  This should be
followed by checking the return value of compat_access_user_space()
for NULL in the callers, at which time the access_ok() in the callers
can also be removed.

Reported-by: Ben Hawkes 
Signed-off-by: H. Peter Anvin 
Acked-by: Benjamin Herrenschmidt 
Acked-by: Chris Metcalf 
Acked-by: David S. Miller 
Acked-by: Ingo Molnar 
Acked-by: Thomas Gleixner 
Acked-by: Tony Luck 
Cc: Andrew Morton 
Cc: Arnd Bergmann 
Cc: Fenghua Yu 
Cc: H. Peter Anvin 
Cc: Heiko Carstens 
Cc: Helge Deller 
Cc: James Bottomley 
Cc: Kyle McMartin 
Cc: Martin Schwidefsky 
Cc: Paul Mackerras 
Cc: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1

2010-08-02T17:21:27+00:00

commit 95e8f634d7a3ea5af40ec3fa42c8a152fd3a0624 upstream.

    In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
    are not currently writeable by the ctc1 instruction.  In odd corner cases,
    this can cause problems.  For example, a case existed where a divide-by-zero
    exception was generated by the FPU, and the signal handler attempted to
    restore the FPU registers to their state before the exception occurred.  In
    this particular setup, writing the old value to the FCSR register would
    cause another divide-by-zero exception to occur immediately.  The solution
    is to change the ctc1 instruction emulator code to allow the Cause bits of
    the FCSR register to be writeable.  This is the behaviour of the hardware
    that the code is emulating.

    This problem was found by Shane McDonald, but the credit for the fix goes
    to Kevin Kissell.  In Kevin's words:

    I submit that the bug is indeed in that ctc_op:  case of the emulator.  The
    Cause bits (17:12) are supposed to be writable by that instruction, but the
    CTC1 emulation won't let them be updated by the instruction.  I think that
    actually if you just completely removed lines 387-388 [...] things would
    work a good deal better.  At least, it would be a more accurate emulation of
    the architecturally defined FPU.  If I wanted to be really, really pedantic
    (which I sometimes do), I'd also protect the reserved bits that aren't
    necessarily writable.

Signed-off-by: Shane McDonald 
To: anemo@mba.ocn.ne.jp
To: kevink@paralogos.com
To: sshtylyov@mvista.com
Patchwork: http://patchwork.linux-mips.org/patch/1205/
Signed-off-by: Ralf Baechle 
Cc: Ben Hutchings 
Signed-off-by: Greg Kroah-Hartman

MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.

2010-05-12T21:57:17+00:00

(cherry picked from commit e65c7f33d75e977350ca350573d93c517ec02776)

Previously it was unconditionally used on all Sibyte family SOCs.  The
M3 bug has to be handled in the TLB exception handler which is extremly
performance sensitive, so this modification is expected to deliver around
2-3% performance improvment.  This is important as required changes to the
M3 workaround will make it more costly.

Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

MIPS: Add missing definition for MADV_HWPOISON.

2009-12-01T16:21:25+00:00

Thanks to Joseph S. Myers for reporting this.

Signed-off-by: Ralf Baechle 
Cc: "Joseph S. Myers" 
Patchwork: http://patchwork.linux-mips.org/patch/723/

MIPS: Fix build error if __xchg() is not getting inlined.

2009-12-01T16:21:25+00:00

If __xchg() is not getting inlined the outline version of the function
will have a reference to __xchg_called_with_bad_pointer() which does not
exist remaining.  Fixed by using BUILD_BUG_ON() to check for allowable
operand sizes.

Signed-off-by: Ralf Baechle 
Patchwork: http://patchwork.linux-mips.org/patch/705/

MIPS: Add DMA declare coherent memory support

2009-11-13T17:10:37+00:00

The ohci-sm501 driver requires dma_declare_coherent_memory().  It is used
by the driver's local memory allocation with dma_alloc_coherent().

Tested on TANBAC TB0287(VR4131 + SM501).

[Ralf: Fixed reject in dma-default.c and removed the entire #if 0'ed block
 in dma-mapping.h instead of just the #if 0.]

Signed-off-by: Yoichi Yuasa 
Signed-off-by: Ralf Baechle

MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store

2009-11-02T11:00:07+00:00

Loongson 2 does not have dcache aliases when is using 16k pages. and the

And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does
not matter here.

Signed-off-by: Zhang Le 
Signed-off-by: Ralf Baechle

MIPS: Avoid potential hazard on Context register

2009-11-02T11:00:07+00:00

set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.

Issue found and fixed for head.S by Chris Dearman .

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: SMTC: Avoid queing multiple reschedule IPIs

2009-11-02T11:00:06+00:00

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle