linux-toradex.git/arch/mips/include/uapi/asm/inst.h, branch v4.4.131 Linux kernel for Apalis and Colibri modules MIPS: inst.h: Add new MIPS R6 FPU opcodes 2015-09-03T10:08:12+00:00 Markos Chandras markos.chandras@imgtec.com 2015-08-13T07:56:27+00:00 107d34009ef00d1680521be2c4a1cba31f9b69a6 Add opcodes for the new MIPS R6 FPU instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10952/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Add opcodes for the new MIPS R6 FPU instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10952/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Declare MSA MI10 instruction formats 2015-09-03T10:07:39+00:00 Leonid Yegoshin Leonid.Yegoshin@imgtec.com 2015-06-22T11:20:58+00:00 6701ca2df4e22fb130330800b6cde687cb761637 Declare a struct describing the MSA MI10 instruction format used for ld & st instructions, for use by subsequent patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10571/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Declare a struct describing the MSA MI10 instruction format used for ld &
st instructions, for use by subsequent patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/10571/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions 2015-02-17T15:37:35+00:00 Markos Chandras markos.chandras@imgtec.com 2015-01-08T11:55:20+00:00 28d6f93d201d20ce47a9e8414655569a78f0353c MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions 2015-02-17T15:37:35+00:00 Markos Chandras markos.chandras@imgtec.com 2014-11-27T09:32:25+00:00 69b9a2fd05a308b9b1e1f282f3b772491603c582 MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Emulate the new MIPS R6 BALC instruction 2015-02-17T15:37:35+00:00 Markos Chandras markos.chandras@imgtec.com 2014-11-26T15:43:11+00:00 84fef630127aa90ef547ddd018d3dc47b1e79a1e MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions 2015-02-17T15:37:34+00:00 Markos Chandras markos.chandras@imgtec.com 2014-11-26T15:03:54+00:00 10d962d5342e84630b258dbd89668c359549b5b5 MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and BNEZLAC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and
BNEZLAC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions 2015-02-17T15:37:34+00:00 Markos Chandras markos.chandras@imgtec.com 2014-11-26T14:08:52+00:00 c893ce38b265d5787d03850b36221f595b224538 MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and BEQZALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Emulate the new MIPS R6 branch compact (BC) instruction 2015-02-17T15:37:34+00:00 Markos Chandras markos.chandras@imgtec.com 2014-11-26T13:56:51+00:00 8467ca0122e20f3f8e73d34907b8b30461af5d4e MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: Emulate the BC1{EQ,NE}Z FPU instructions 2015-02-17T15:37:32+00:00 Markos Chandras markos.chandras@imgtec.com 2014-11-26T10:10:18+00:00 c8a34581ec09a5ee11dd833d6c5cf41fdbef706f MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 introduced the following two branch instructions for COP1:

BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero
BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS: mm: Add MIPS R6 instruction encodings 2015-02-16T14:02:50+00:00 Leonid Yegoshin Leonid.Yegoshin@imgtec.com 2014-11-19T09:29:42+00:00 a168b8f1cde6588ff7a67699fa11e01bc77a5ddd MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> 
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>