linux-toradex.git/arch/mips/include, branch v2.6.32.15

MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.

2010-05-12T21:57:17+00:00

(cherry picked from commit e65c7f33d75e977350ca350573d93c517ec02776)

Previously it was unconditionally used on all Sibyte family SOCs.  The
M3 bug has to be handled in the TLB exception handler which is extremly
performance sensitive, so this modification is expected to deliver around
2-3% performance improvment.  This is important as required changes to the
M3 workaround will make it more costly.

Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

MIPS: Add missing definition for MADV_HWPOISON.

2009-12-01T16:21:25+00:00

Thanks to Joseph S. Myers for reporting this.

Signed-off-by: Ralf Baechle 
Cc: "Joseph S. Myers" 
Patchwork: http://patchwork.linux-mips.org/patch/723/

MIPS: Fix build error if __xchg() is not getting inlined.

2009-12-01T16:21:25+00:00

If __xchg() is not getting inlined the outline version of the function
will have a reference to __xchg_called_with_bad_pointer() which does not
exist remaining.  Fixed by using BUILD_BUG_ON() to check for allowable
operand sizes.

Signed-off-by: Ralf Baechle 
Patchwork: http://patchwork.linux-mips.org/patch/705/

MIPS: Add DMA declare coherent memory support

2009-11-13T17:10:37+00:00

The ohci-sm501 driver requires dma_declare_coherent_memory().  It is used
by the driver's local memory allocation with dma_alloc_coherent().

Tested on TANBAC TB0287(VR4131 + SM501).

[Ralf: Fixed reject in dma-default.c and removed the entire #if 0'ed block
 in dma-mapping.h instead of just the #if 0.]

Signed-off-by: Yoichi Yuasa 
Signed-off-by: Ralf Baechle

MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store

2009-11-02T11:00:07+00:00

Loongson 2 does not have dcache aliases when is using 16k pages. and the

And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does
not matter here.

Signed-off-by: Zhang Le 
Signed-off-by: Ralf Baechle

MIPS: Avoid potential hazard on Context register

2009-11-02T11:00:07+00:00

set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.

Issue found and fixed for head.S by Chris Dearman .

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: SMTC: Avoid queing multiple reschedule IPIs

2009-11-02T11:00:06+00:00

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: GIC: Random fixes and enhancements.

2009-11-02T11:00:06+00:00

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: SPRAM: Clean up support code a little

2009-11-02T11:00:05+00:00

Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: Fix machine check exception in kmap_coherent()

2009-11-02T11:00:04+00:00

On an SMP system with cache aliases, the following sequence of events may
happen:

1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a
   temporary mapping in the fixmap region
2) copy_page() starts on CPU0
3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page()
4) CPU0 takes the interrupt, interrupting copy_page()
5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again
6) The second invocation of kmap_coherent() on CPU0 tries to use the
   same fixmap virtual address that was being used by copy_user_highpage()
7) CPU0 throws a machine check exception for the TLB address conflict

Fixed by creating an extra set of fixmap entries for use in interrupt
handlers.  This prevents fixmap VA conflicts between copy_user_highpage()
running in user context, and local_r4k_flush_cache_page() invoked from an
SMP IPI.

Signed-off-by: Kevin Cernekee 
Signed-off-by: Ralf Baechle