linux-toradex.git/arch/mips/include, branch v4.0-rc2

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2015-02-22T03:41:38+00:00

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS:

   - a number of fixes that didn't make the 3.19 release.

   - a number of cleanups.

   - preliminary support for Cavium's Octeon 3 SOCs which feature up to
     48 MIPS64 R3 cores with FPU and hardware virtualization.

   - support for MIPS R6 processors.

     Revision 6 of the MIPS architecture is a major revision of the MIPS
     architecture which does away with many of original sins of the
     architecture such as branch delay slots.  This and other changes in
     R6 require major changes throughout the entire MIPS core
     architecture code and make up for the lion share of this pull
     request.

   - finally some preparatory work for eXtendend Physical Address
     support, which allows support of up to 40 bit of physical address
     space on 32 bit processors"

     [ Ahh, MIPS can't leave the PAE brain damage alone.  It's like
       every CPU architect has to make that mistake, but pee in the snow
       by changing the TLA.  But whether it's called PAE, LPAE or XPA,
       it's horrid crud   - Linus ]

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits)
  MIPS: sead3: Corrected get_c0_perfcount_int
  MIPS: mm: Remove dead macro definitions
  MIPS: OCTEON: irq: add CIB and other fixes
  MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.
  MIPS: OCTEON: More OCTEONIII support
  MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.
  MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.
  MIPS: OCTEON: Update octeon-model.h code for new SoCs.
  MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX
  MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h
  MIPS: OCTEON: Implement the core-16057 workaround
  MIPS: OCTEON: Delete unused COP2 saving code
  MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
  MIPS: OCTEON: Save and restore CP2 SHA3 state
  MIPS: OCTEON: Fix FP context save.
  MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs
  MIPS: boot: Provide more uImage options
  MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h
  MIPS: ip22-gio: Remove legacy suspend/resume support
  mips: pci: Add ifdef around pci_proc_domain
  ...

MIPS: OCTEON: More OCTEONIII support

2015-02-20T14:32:46+00:00

Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.

Signed-off-by: Chandrakala Chavva 
Signed-off-by: Aleksey Makarov 
Signed-off-by: David Daney 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8945/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.

2015-02-20T14:32:22+00:00

CN38XX pass 1 required icache prefetching to be turned off. This chip never
reached production and is long dead. Other processor specific icache settings
are done by the bootloader. Remove these bits from the kernel.

Signed-off-by: Chad Reese 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney 
Patchwork: https://patchwork.linux-mips.org/patch/8944/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.

2015-02-20T14:31:59+00:00

Signed-off-by: David Daney 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8943/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Update octeon-model.h code for new SoCs.

2015-02-20T14:31:43+00:00

Add coverage for OCTEON III models.

Signed-off-by: David Daney 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8942/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX

2015-02-20T14:31:27+00:00

Make messages refer to all CN6XXX.

Signed-off-by: David Daney 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h

2015-02-20T14:31:07+00:00

Also update union octeon_cvmemctl with new OCTEON II fields.

[aleksey.makarov@auriga.com: use __BITFIELD_FIELD]

Signed-off-by: David Daney 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8940/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Implement the core-16057 workaround

2015-02-20T14:30:42+00:00

Disable ICache prefetch for certian Octeon II processors.

Signed-off-by: David Daney 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8938/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Save and restore CP2 SHA3 state

2015-02-20T14:29:08+00:00

Allocate new save space, and then save/restore the registers if
OCTEON III.

Signed-off-by: David Daney 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8935/
Signed-off-by: Ralf Baechle

MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs

2015-02-20T14:28:29+00:00

The wide multiplier is twice as wide, so we need to save twice as much
state.  Detect the multiplier type (CPU type) at start up and install
model specific handlers.

[aleksey.makarov@auriga.com:
	conflict resolution,
	support for old compilers]

Signed-off-by: David Daney 
Signed-off-by: Leonid Rosenboim 
Signed-off-by: Aleksey Makarov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8933/
Signed-off-by: Ralf Baechle