linux-toradex.git/arch/mips/kernel/cevt-r4k.c, branch v3.2.11

MIPS: Kernel hangs occasionally during boot.

2011-11-08T17:59:22+00:00

The Kernel hangs occasionally during boot after "Calibrating delay loop..".
This is caused by the c0_compare_int_usable() routine in cevt-r4k.c
returning false which causes the system to disable the timer and hang later.
The false return happens because the routine is using a series of four calls
to irq_disable_hazard() as a delay while it waits for the timer changes to
propagate to the cp0 cause register. On newer MIPS cores, like the 74K, the
series of irq_disable_hazard() calls turn into ehb instructions and can take
as little as a few clock ticks for all 4 instructions. This is not enough of
a delay, so the routine thinks the timer is not working.  This fix uses up
to a max number of cycle counter ticks for the delay and uses
back_to_back_c0_hazard() instead of irq_disable_hazard() to handle the
hazard condition between cp0 writes and cp0 reads.

Signed-off-by: Al Cooper 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2911/
Signed-off-by: Ralf Baechle

MIPS: Fix CP0 COUNTER clockevent race

2010-12-16T18:10:58+00:00

Consider the following test case:

write_c0_compare(read_c0_count());

Even if the counter doesn't increment during execution, this might not
generate an interrupt until the counter wraps around.  The CPU may
perform the comparison each time CP0 COUNT increments, not when CP0
COMPARE is written.

If mips_next_event() is called with a very small delta, and CP0 COUNT
increments during the calculation of "cnt += delta", it is possible
that CP0 COMPARE will be written with the current value of CP0 COUNT.
If this is detected, the function should return -ETIME, to indicate
that the interrupt might not have actually gotten scheduled.

Signed-off-by: Kevin Cernekee 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1836/
Signed-off-by: Ralf Baechle

MIPS: Add missing #inclusions of

2010-10-07T13:08:54+00:00

Add missing #inclusions of  to a whole bunch of files that should
really include it.  Note that this can replace #inclusions of .

This is required for the patch to sort out irqflags handling function naming to
compile on MIPS.

The problem is that these files require access to things like setup_irq() -
which isn't available by #including 

Signed-off-by: David Howells 
Acked-by: Ralf Baechle

MIPS: Don't overflow cevt-r4k.c calculations at high clock rates.

2010-08-05T12:25:39+00:00

The 'mult' element of struct clock_event_device must never be wider
than 32-bits.  If it were, it would get truncated when used by
clockevent_delta2ns() when this calls do_div().

We can meet this requirement by using clockevent_set_clock() to set
the MULT and SHIFT values.

Signed-off-by: David Daney 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1253/
Acked-by: Thomas Gleixner 
Signed-off-by: Ralf Baechle

MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs

2010-01-27T23:03:31+00:00

The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/
Signed-off-by: Ralf Baechle

MIPS: Add IRQF_TIMER flag for timer interrupts

2009-11-02T11:00:02+00:00

Along the lines of d6c585a4342a2ff627a29f9aea77c5ed4cd76023, add IRQF_TIMER
flag for all timer interrupts  This ensures that timer interrupts won't be
disabled on suspend and not threaded for PREEMPT_RT.

Signed-off-by: Wu Zhangjin 
Acked-by: Thomas Gleixner 
Signed-off-by: Ralf Baechle

MIPS: Build fix - include into all smp_processor_id() users.

2009-06-24T17:34:39+00:00

Some of the were relying into smp.h being dragged in by another header
which of course is fragile.   uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.

Signed-off-by: Ralf Baechle

MIPS: make cp0 counter clocksource/event usable as fallback.

2009-01-11T09:57:26+00:00

The current mips clock build infrastructure lets a system only use
either the MIPS cp0 counter or a SoC specific timer as a clocksource /
clockevent device.

This patch renames the core cp0 counter clocksource / clockevent functions
from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to
call these renamed functions instead.

Chips which can detect whether it is safe to use a chip-specific timer
can now fall back on the cp0 counter if necessary and possible
(e.g. Alchemy with a follow-on patch).

Existing behaviour is not changed in any way.

Signed-off-by: Manuel Lauss 
Signed-off-by: Ralf Baechle

cpumask: convert struct clock_event_device to cpumask pointers.

2008-12-13T10:50:26+00:00

Impact: change calling convention of existing clock_event APIs

struct clock_event_timer's cpumask field gets changed to take pointer,
as does the ->broadcast function.

Another single-patch change.  For safety, we BUG_ON() in
clockevents_register_device() if it's not set.

Signed-off-by: Rusty Russell 
Cc: Ingo Molnar

[MIPS] SMTC: Fix SMTC dyntick support.

2008-10-03T16:58:58+00:00

Rework of SMTC support to make it work with the new clock event system,
allowing "tickless" operation, and to make it compatible with the use of
the "wait_irqoff" idle loop.  The new clocking scheme means that the
previously optional IPI instant replay mechanism is now required, and has
been made more robust.

Signed-off-by: Kevin D. Kissell 
Signed-off-by: Ralf Baechle