linux-toradex.git/arch/mips/kernel/cpu-probe.c, branch v4.4.106

MIPS: Extend hardware table walking support to MIPS64

2015-11-11T07:35:54+00:00

Extend the existing support for Hardware Table Walking (HTW) to MIPS64
systems by supporting PMDs & setting the pointer size bit in PWSize,
then ceasing to blacklist HTW on MIPS64 systems.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill 
Cc: Joshua Kinard 
Cc: Leonid Yegoshin 
Cc: Maciej W. Rozycki 
Cc: Paul Gortmaker 
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11224/
Signed-off-by: Ralf Baechle

MIPS: Fix FTLB detection for R6

2015-09-22T19:11:39+00:00

R6 removed the Config4.MMUExtDef field, with the low 16 bits only
allowed to contain FTLB fields, and commit e87569cd6c57 ("MIPS:
cpu-probe: Fix VTLB/FTLB configuration for R6") updated the probing of
this field to assume an FTLB is always present for R6.

However the FTLB may still be absent. The presence of those fields is
actually specified by the MMU type in the Config.MT field, so use that
(the new cpu_has_ftlb) to determine whether the FTLB is actually
present.

Fixes: e87569cd6c57 ("MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6")
Signed-off-by: James Hogan 
Cc: Ralf Baechle 
Cc: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11160/
Signed-off-by: Ralf Baechle

MIPS: cpu-features: Add cpu_has_ftlb

2015-09-22T19:11:05+00:00

Add cpu_has_ftlb, which specifies that an FTLB is present in addition to
the VTLB, probed based on whether Config.MT == 4 (rather than 1 for
standard JTLB).

This is necessary since MIPS release 6 removes Config4.MMUExtDef, so the
presence of the FTLB fields in Config4 must be determined from Config.MT
instead.

Signed-off-by: James Hogan 
Cc: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11159/
Signed-off-by: Ralf Baechle

MIPS: Advertise MSA support via HWCAP when present

2015-09-03T10:08:00+00:00

If MSA is supported by both the hardware & the kernel then advertise
that support to userland via the AT_HWCAP aux vector.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: Maciej W. Rozycki 
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10799/
Signed-off-by: Ralf Baechle

MIPS: Advertise MIPSr6 via HWCAP when appropriate

2015-09-03T10:07:59+00:00

When running on a CPU implementing the release 6 of the MIPS32 or MIPS64
ISA, advertise that to userland via the appropriate HWCAP bit.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: Maciej W. Rozycki 
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10798/
Signed-off-by: Ralf Baechle

MIPS: AT_HWCAP aux vector infrastructure

2015-09-03T10:07:59+00:00

In order for userland to determine whether various features are safe to
use, it will need to know both that the hardware supports those features
and that the kernel is recent enough & configured appropriately to
support them. For example under the O32 modeless FP proposal the dynamic
linker & ifunc resolvers will need this information.  The kernel is the
only thing in a position to know availability accurately, so the kernel
needs to provide the information to userland. This patch introduces the
infrastructure to provide the AT_HWCAP aux vector to userland in order
to provide that information. It also defines the 2 currently specified
flags, which indicate MIPSr6 & MSA support.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Kees Cook 
Cc: Huacai Chen 
Cc: Maciej W. Rozycki 
Cc: Alex Smith 
Cc: linux-kernel@vger.kernel.org
Cc: Leonid Yegoshin 
Cc: Markos Chandras 
Cc: Ingo Molnar 
Patchwork: https://patchwork.linux-mips.org/patch/10797/
Signed-off-by: Ralf Baechle

MIPS: Probe for small (1KiB) page support

2015-09-03T10:07:47+00:00

Probe Config3 for small page support. This will be useful to give clues
as to whether the PageGrain register exists.

Signed-off-by: James Hogan 
Cc: Maciej W. Rozycki 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10722/
Signed-off-by: Ralf Baechle

MIPS: Set up FTLB probability for I6400

2015-08-26T13:23:22+00:00

Set up the I6400 FTLB probability similar to P5600 and proAptiv.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10652/
Signed-off-by: Ralf Baechle

MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6

2015-08-26T13:23:21+00:00

R6 has dropped the MMUExtDef field from the config4 register and it
now returns 0. However, the return value means nothing in that case
and the only supported configuration for R6 is the VTLB+FTLB
(MMUextDef == 3). As a result, rework the code so that the correct
value is set for R6 cores.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10651/
Signed-off-by: Ralf Baechle

MIPS: Add default case for the FTLB enable/disable code

2015-08-26T13:23:18+00:00

Add a default case for the FTLB enable/disable code. This will be used
to detect that something went wrong in the set_ftlb_enable() function
either because that function knows nothing about the running core, or
simply because the core can't turn its FTLB on/off.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10650/
Signed-off-by: Ralf Baechle