linux-toradex.git/arch/mips/kernel/idle.c, branch v4.4.85

Merge branch '4.3-fixes' into mips-for-linux-next

2015-11-12T10:36:03+00:00

MIPS: idle: add case for CPU_5KE

2015-11-12T10:35:48+00:00

While the 5KE processors have never been taped out, they exists though
a CP0.PRId and experimental RTLs or QEMU implementations. Add a case
entry in the idle code, as they can use the standard idle loop like the
5K processors.

Signed-off-by: Aurelien Jarno 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11099/
Signed-off-by: Ralf Baechle

MIPS: Always use r4k_wait_irqoff for MIPSr6

2015-11-11T07:35:23+00:00

Prior to release 6 of the MIPS architecture it has been implementation
dependent whether masked interrupts cause a wait instruction to return,
so the kernel has effectively had to maintain a whitelist of cores upon
which it is safe to use the r4k_wait_irqoff cpu_wait implementation.
With MIPSr6 this is no longer implementation dependent and
r4k_wait_irqoff can always be used.

Remove the existing I6400 case which will no longer ever be hit, and was
incorrect anyway since I6400 & r6 in general doesn't have the WII bit.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin 
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11210/
Signed-off-by: Ralf Baechle

MIPS: Switch BMIPS5000 to use r4k_wait_irqoff()

2015-11-09T09:20:43+00:00

BCM7425 CPU Interface Zephyr Processor, pages 5-309 and 5-310
BCM7428B0 CPU Interface Zephyr Processor, pages 5-337 and 5-338

WAIT instruction:
Thread enters wait state. No instructions are executed until an
interrupt occurs. The processor's clocks are stopped if both threads
are in idle mode.

Description:
Execution of this instruction puts the thread into wait state, an idle
mode in which no instructions are fetched or executed. The thread remains
in wait state until an interrupt occurs that is not masked by the
interrupt mask field in the Status register. Then, if interrupts are
enabled by the IE bit in the Status register, the interrupt is serviced.
The ERET instruction returns to the instruction following the WAIT
instruction. If interrupts are disabled, the processor resumes executing
instructions with the next sequential instruction.

Programming notes:
The WAIT instruction should be executed while interrupts are disabled
by the IE bit in the Status register. This avoids a potential timing
hazard, which occurs if an interrupt is taken between testing the counter
and executing the WAIT instruction. In this hazard case, the interrupt
will have been completed before the WAIT instruction is executed, so
the processor will remain indefinitely in wait state until the next
interrupt.

Signed-off-by: Petri Gynther 
Reviewed-by: Florian Fainelli 
Cc: cernekee@gmail.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11322/
Signed-off-by: Ralf Baechle

MIPS: Add cases for CPU_I6400

2015-08-26T13:23:03+00:00

Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10635/
Signed-off-by: Ralf Baechle

MIPS: idle: Workaround wait + FDC problems

2015-03-31T10:04:12+00:00

On certain cores (namely proAptiv and P5600) incoming data via a Fast
Debug Channel (FDC) while the core is blocked on a wait instruction will
cause the wait not to wake up even when another interrupt is received.
This makes an idle target stop as soon as you send FDC data to it, until
the debug probe interrupts it and restarts the wait instruction.

This is worked around by avoiding using r4k_wait on these cores if
CONFIG_MIPS_EJTAG_FDC_TTY is enabled (which would imply the user intends
to use the FDC).

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: James Hogan 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9144/
Signed-off-by: Ralf Baechle

MIPS: Add cases for CPU_QEMU_GENERIC

2015-02-16T10:01:24+00:00

Add a CPU_QEMU_GENERIC case to various switch statements.

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras

MIPS: idle: Remove leftover __pastwait symbol and its references

2014-10-23T17:24:05+00:00

The __pastwait symbol was only used by the address_is_in_r4k_wait_irqoff
function but this is no longer used since the SMTC removal in commit
b633648c5ad3 ('MIPS: MT: Remove SMTC support'). That symbol also led to
build failures under certain random configuration due to the way the
compiler compiled the r4k_wait_irqoff function. If that function was
called multiple times, the __pastwait symbol was redefined breaking the
build like this:

CHK     include/generated/compile.h
CC      arch/mips/kernel/idle.o
{standard input}: Assembler messages:
{standard input}:527: Error: symbol `__pastwait' is already defined

Link: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1244879922.24479.30.camel%40falcon
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/7791/
Signed-off-by: Ralf Baechle

Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into mips-for-linux-next

2014-05-29T13:08:23+00:00

MIPS: cpuidle wait instruction state

2014-05-28T15:20:34+00:00

Defines a macro intended to allow trivial use of the regular MIPS wait
instruction from cpuidle drivers, which may simply invoke the macro
within their array of states.

Signed-off-by: Paul Burton