linux-toradex.git/arch/mips/kernel/mips-cm.c, branch v4.9.88

tree-wide: replace config_enabled() with IS_ENABLED()

2016-08-04T12:50:07+00:00

The use of config_enabled() against config options is ambiguous.  In
practical terms, config_enabled() is equivalent to IS_BUILTIN(), but the
author might have used it for the meaning of IS_ENABLED().  Using
IS_ENABLED(), IS_BUILTIN(), IS_MODULE() etc.  makes the intention
clearer.

This commit replaces config_enabled() with IS_ENABLED() where possible.
This commit is only touching bool config options.

I noticed two cases where config_enabled() is used against a tristate
option:

 - config_enabled(CONFIG_HWMON)
  [ drivers/net/wireless/ath/ath10k/thermal.c ]

 - config_enabled(CONFIG_BACKLIGHT_CLASS_DEVICE)
  [ drivers/gpu/drm/gma500/opregion.c ]

I did not touch them because they should be converted to IS_BUILTIN()
in order to keep the logic, but I was not sure it was the authors'
intention.

Link: http://lkml.kernel.org/r/1465215656-20569-1-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada 
Acked-by: Kees Cook 
Cc: Stas Sergeev 
Cc: Matt Redfearn 
Cc: Joshua Kinard 
Cc: Jiri Slaby 
Cc: Bjorn Helgaas 
Cc: Borislav Petkov 
Cc: Markos Chandras 
Cc: "Dmitry V. Levin" 
Cc: yu-cheng yu 
Cc: James Hogan 
Cc: Brian Gerst 
Cc: Johannes Berg 
Cc: Peter Zijlstra 
Cc: Al Viro 
Cc: Will Drewry 
Cc: Nikolay Martynov 
Cc: Huacai Chen 
Cc: "H. Peter Anvin" 
Cc: Thomas Gleixner 
Cc: Daniel Borkmann 
Cc: Leonid Yegoshin 
Cc: Rafal Milecki 
Cc: James Cowgill 
Cc: Greg Kroah-Hartman 
Cc: Ralf Baechle 
Cc: Alex Smith 
Cc: Adam Buchbinder 
Cc: Qais Yousef 
Cc: Jiang Liu 
Cc: Mikko Rapeli 
Cc: Paul Gortmaker 
Cc: Denys Vlasenko 
Cc: Brian Norris 
Cc: Hidehiro Kawai 
Cc: "Luis R. Rodriguez" 
Cc: Andy Lutomirski 
Cc: Ingo Molnar 
Cc: Dave Hansen 
Cc: "Kirill A. Shutemov" 
Cc: Roland McGrath 
Cc: Paul Burton 
Cc: Kalle Valo 
Cc: Viresh Kumar 
Cc: Tony Wu 
Cc: Huaitong Han 
Cc: Sumit Semwal 
Cc: Alexei Starovoitov 
Cc: Juergen Gross 
Cc: Jason Cooper 
Cc: "David S. Miller" 
Cc: Oleg Nesterov 
Cc: Andrea Gelmini 
Cc: David Woodhouse 
Cc: Marc Zyngier 
Cc: Rabin Vincent 
Cc: "Maciej W. Rozycki" 
Cc: David Daney 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

MIPS: Fix misspellings in comments.

2016-04-03T10:32:09+00:00

Signed-off-by: Adam Buchbinder 
Cc: linux-mips@linux-mips.org
Cc: trivial@kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12617/
Signed-off-by: Ralf Baechle

MIPS: CM, CPC: Ensure core-other GCRs reflect the correct core

2015-11-11T07:35:18+00:00

Ensure the update to which core the core-other GCR regions reflect has
taken place before any core-other GCRs are accessed by placing a memory
barrier (sync instruction) between the write to the core-other registers
and any such GCR accesses.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Bjorn Helgaas 
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11209/
Signed-off-by: Ralf Baechle

MIPS: CM: Introduce core-other locking functions

2015-11-11T07:35:14+00:00

Introduce mips_cm_lock_other & mips_cm_unlock_other, mirroring the
existing CPC equivalents, in order to lock access from the current core
to another via the core-other GCR region. This hasn't been required in
the past but with CM3 the CPC starts using GCR_CL_OTHER rather than
CPC_CL_OTHER and this will be required for safety.

[ralf@linux-mips.org: Fix merge conflict.]

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11207/
Signed-off-by: Ralf Baechle

MIPS: Always read full 64 bit CM error GCRs for CM3

2015-10-26T08:49:47+00:00

CM3 has 64 bit GCR_ERROR_* registers, but the code in
mips_cm_error_report was previously only reading 32 bits of it in MIPS32
kernels. Fix by splitting the reads for CM2 & CM3, and making use of the
read64_ variants of the accessor function for CM3.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11189/
Signed-off-by: Ralf Baechle

MIPS: Avoid buffer overrun in mips_cm_error_report

2015-10-26T08:49:46+00:00

Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache
errors") added cases for decoding errors reported by CM3, but leaves the
buf variable which is printed as a string uninitialised for cause values
other than 1, 2 or 3. Fix by ensuring the buf variable is initialised to
an empty string in such cases.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras 
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11187/
Signed-off-by: Ralf Baechle

MIPS: Don't read GCRs when a CM is not present

2015-10-26T08:49:46+00:00

Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache
errors") leads to Malta boards unconditionally reading CM GCRs upon bus
errors, regardless of whether a CM is present. This is incorrect & will
lead to further exceptions. Fix by moving the GCR reads to after the
check for whether a CM is present.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras 
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11186/
Signed-off-by: Ralf Baechle

MIPS: CM: Add support for reporting CM cache errors

2015-08-26T13:23:15+00:00

The CM cache error reporting code is not Malta specific and as such it
should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the
way cache errors are being recorded to the registers so extend the
previous code to add support for the CM3 as well.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10646/
Signed-off-by: Ralf Baechle

MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.

2015-08-26T13:23:14+00:00

The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64
so we change its type to unsigned long.

Signed-off-by: Markos Chandras 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10644/
Signed-off-by: Ralf Baechle

MIPS: mips-cm: Extend CM accessors for 64-bit CPUs

2015-08-26T13:23:12+00:00

Previously, the CM accessors were only accessing CM registers as u32
types instead of using the native CM register with. However, newer CMs
may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs
(CM3) hold all the useful configuration bits in the lower half of the
64-bit registers (at least most of them) so they can still be accessed
using the current 32-bit accessors.

Signed-off-by: Markos Chandras 
Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Andrew Bresticker 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10707/
Signed-off-by: Ralf Baechle