linux-toradex.git/arch/mips/kernel/r4k_fpu.S, branch v4.19

MIPS: Fix MIPS64 FP save/restore on 32-bit kernels

2017-11-09T14:13:40+00:00

32-bit kernels can be configured to support MIPS64, in which case
neither CONFIG_64BIT or CONFIG_CPU_MIPS32_R* will be set. This causes
the CP0_Status.FR checks at the point of floating point register save
and restore to be compiled out, which results in odd FP registers not
being saved or restored to the task or signal context even when
CP0_Status.FR is set.

Fix the ifdefs to use CONFIG_CPU_MIPSR2 and CONFIG_CPU_MIPSR6, which are
enabled for the relevant revisions of either MIPS32 or MIPS64, along
with some other CPUs such as Octeon (r2), Loongson1 (r2), XLP (r2),
Loongson 3A R2.

The suspect code originates from commit 597ce1723e0f ("MIPS: Support for
64-bit FP with O32 binaries") in v3.14, however the code in
__enable_fpu() was consistent and refused to set FR=1, falling back to
software FPU emulation. This was suboptimal but should be functionally
correct.

Commit fcc53b5f6c38 ("MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6
CPU") in v4.2 (and stable tagged back to 4.0) later introduced the bug
by updating __enable_fpu() to set FR=1 but failing to update the other
similar ifdefs to enable FR=1 state handling.

Fixes: fcc53b5f6c38 ("MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPU")
Signed-off-by: James Hogan 
Cc: Ralf Baechle 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc:  # 4.0+
Patchwork: https://patchwork.linux-mips.org/patch/16739/

MIPS: Move r4k FP code from r4k_switch.S to r4k_fpu.S

2017-08-29T13:21:51+00:00

Move _save_fp(), _restore_fp(), _save_msa(), _restore_msa(),
_init_msa_upper() & _init_fpu() out of r4k_switch.S & into r4k_fpu.S.
This allows us to clean up the way in which Octeon includes the default
r4k implementations of these FP functions despite replacing resume(),
and makes CONFIG_R4K_FPU more straightforwardly represent all
configurations that have an R4K-style FPU, including Octeon.

Besides cleaning up this will be useful for later patches which disable
FP support.

[ralf@linux-mips.org: Fixed build issues reported by Arnd Bergmann
]

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16237/
Signed-off-by: Ralf Baechle

MIPS: Use copy_s.fmt rather than copy_u.fmt

2016-05-09T10:00:04+00:00

In revision 1.12 of the MSA specification, the copy_u.w instruction has
been removed for MIPS32 & the copy_u.d instruction has been removed for
MIPS64. Newer toolchains (eg. Codescape SDK essentials 2015.10) will
complain about this like so:

arch/mips/kernel/r4k_fpu.S:290: Error: opcode not supported on this
processor: mips32r2 (mips32r2) `copy_u.w $1,$w26[3]'

Since we always copy to the width of a GPR, simply use copy_s instead of
copy_u to fix this.

Signed-off-by: Paul Burton 
Signed-off-by: James Hogan 
Cc: linux-mips@linux-mips.org
Cc:  # 4.3.x+
Patchwork: https://patchwork.linux-mips.org/patch/13061/
Signed-off-by: Ralf Baechle

MIPS: Avoid variant of .type unsupported by LLVM Assembler

2016-02-29T10:23:49+00:00

The target independent parts of the LLVM Lexer considers 'fault@function'
to be a single token representing the 'fault' symbol with a 'function'
modifier. However, this is not the case in the .type directive where
'function' refers to STT_FUNC from the ELF standard.

Although GAS accepts it, '.type symbol@function' is an undocumented form of
this directive. The documentation specifies a comma between the symbol and
'@function'.

Signed-off-by: Scott Egerton 
Signed-off-by: Daniel Sanders 
Reviewed-by: Maciej W. Rozycki 
Cc: Paul Burton 
Cc: Leonid Yegoshin 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12587/
Signed-off-by: Ralf Baechle

MIPS: Save MSA extended context around signals

2015-09-03T10:07:59+00:00

It is desirable for signal handlers to be allowed to make use of MSA,
particularly if auto vectorisation is used when compiling a program.
The MSA context must therefore be saved & restored before & after
invoking the signal handler. Make use of the extended context structs
defined in the preceding patch to save MSA context after the sigframe
when appropriate.

[ralf@linux-mips.org: Fixed conflicts.]

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: linux-kernel@vger.kernel.org
Cc: Richard Weinberger 
Cc: James Hogan 
Cc: Andrew Morton 
Cc: Andy Lutomirski 
Cc: Markos Chandras 
Cc: Manuel Lauss 
Cc: Maciej W. Rozycki 
Patchwork: https://patchwork.linux-mips.org/patch/10796/
Signed-off-by: Ralf Baechle

MIPS: Use common FP sigcontext code for O32 compat

2015-09-03T10:07:56+00:00

Make use of the common FP sigcontext code for O32 binaries running on
MIPS64 kernels now that it is taking appropriate offsets into struct
sigcontext(32) from struct mips_abi.

[ralf@linux-mips.org: Fixed reject.]

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: Michael Ellerman 
Cc: linux-kernel@vger.kernel.org
Cc: Richard Weinberger 
Cc: James Hogan 
Cc: Andrew Morton 
Cc: Andy Lutomirski 
Cc: Markos Chandras 
Cc: Manuel Lauss 
Cc: Maciej W. Rozycki 
Patchwork: https://patchwork.linux-mips.org/patch/10792/
Signed-off-by: Ralf Baechle

MIPS: Use struct mips_abi offsets to save FP context

2015-09-03T10:07:55+00:00

When saving FP state to struct sigcontext, make use of the offsets
provided by struct mips_abi to obtain appropriate addresses for the
sc_fpregs & sc_fpc_csr fields of the sigcontext. This is done only for
the native struct sigcontext in this patch (ie. for O32 in CONFIG_32BIT
kernels or for N64 in CONFIG_64BIT kernels) but is done in preparation
for sharing this code with compat ABIs in further patches.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: linux-kernel@vger.kernel.org
Cc: Richard Weinberger 
Cc: James Hogan 
Cc: Andy Lutomirski 
Cc: Markos Chandras 
Cc: Manuel Lauss 
Cc: Maciej W. Rozycki 
Patchwork: https://patchwork.linux-mips.org/patch/10789/
Signed-off-by: Ralf Baechle

MIPS: Introduce accessors for MSA vector registers

2015-09-03T10:07:40+00:00

Introduce accessor functions allowing the kernel to access arbitrary
vector registers using an arbitrary data format. The accessors are
implemented in assembly, using macros to avoid massive duplication, in
order to make use of the existing support for MSA with & without
toolchain support. The accessors will be used in a later patch.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin 
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Cc: Manuel Lauss 
Patchwork: https://patchwork.linux-mips.org/patch/10572/
Signed-off-by: Ralf Baechle

MIPS: Push .set mips64r* into the functions needing it

2015-03-27T18:42:42+00:00

The {save,restore}_fp_context{,32} functions require that the assembler
allows the use of sdc instructions on any FP register, and this is
acomplished by setting the arch to mips64r2 or mips64r6
(using MIPS_ISA_ARCH_LEVEL_RAW).

However this has the effect of enabling the assembler to use mips64
instructions in the expansion of pseudo-instructions. This was done in
the (now-reverted) commit eec43a224cf1 "MIPS: Save/restore MSA context
around signals" which led to my mistakenly believing that there was an
assembler bug, when in reality the assembler was just emitting mips64
instructions. Avoid the issue for future commits which will add code to
r4k_fpu.S by pushing the .set MIPS_ISA_ARCH_LEVEL_RAW directives into
the functions that require it, and remove the spurious assertion
declaring the assembler bug.

Signed-off-by: Paul Burton 
[james.hogan@imgtec.com: Rebase on v4.0-rc1 and reword commit message to
 reflect use of MIPS_ISA_ARCH_LEVEL_RAW]
Signed-off-by: James Hogan 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9612/
Signed-off-by: Ralf Baechle

MIPS: kernel: r4k_fpu: Add support for MIPS R6

2015-02-17T15:37:27+00:00

Add the MIPS R6 related preprocessor definitions for FPU signal
related functions. MIPS R6 only has FR=1 so avoid checking that
bit on the C0/Status register.

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras